?? hc.vhd
字號(hào):
--***************************************************************************
--* *
--* Copyright (C) 1987-1995 *
--* by OrCAD, INC. *
--* *
--* All rights reserved. *
--* *
--***************************************************************************
-- Purpose: OrCAD VHDL Source File
-- Version: v7.00.01
-- Date: February 24, 1997
-- File: HC.VHD
-- Resource: National, 1984 Logic Databook
-- Delay units: Picoseconds
-- Characteristics: 74HCXXX Tplh and Tphl, 15pF and 50pF
-- Rev Notes:
-- x7.00.00 - Handle feedback in correct manner for Simulate v7.0
-- v7.00.01 - Fixed components with Px port names.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC00\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I1_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC00\;
ARCHITECTURE model OF \74HC00\ IS
BEGIN
O_A <= NOT ( A_A AND I1_A ) AFTER 1500 ps;
O_B <= NOT ( A_B AND I1_B ) AFTER 1500 ps;
O_C <= NOT ( A_C AND I1_C ) AFTER 1500 ps;
O_D <= NOT ( A_D AND I1_D ) AFTER 1500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC00A\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I1_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC00A\;
ARCHITECTURE model OF \74HC00A\ IS
BEGIN
O_A <= NOT ( A_A AND I1_A ) AFTER 1500 ps;
O_B <= NOT ( A_B AND I1_B ) AFTER 1500 ps;
O_C <= NOT ( A_C AND I1_C ) AFTER 1500 ps;
O_D <= NOT ( A_D AND I1_D ) AFTER 1500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC02\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I1_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC02\;
ARCHITECTURE model OF \74HC02\ IS
BEGIN
O_A <= NOT ( A_A OR I1_A ) AFTER 1500 ps;
O_B <= NOT ( A_B OR I1_B ) AFTER 1500 ps;
O_C <= NOT ( A_C OR I1_C ) AFTER 1500 ps;
O_D <= NOT ( A_D OR I1_D ) AFTER 1500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC02A\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I1_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC02A\;
ARCHITECTURE model OF \74HC02A\ IS
BEGIN
O_A <= NOT ( A_A OR I1_A ) AFTER 1500 ps;
O_B <= NOT ( A_B OR I1_B ) AFTER 1500 ps;
O_C <= NOT ( A_C OR I1_C ) AFTER 1500 ps;
O_D <= NOT ( A_D OR I1_D ) AFTER 1500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC03\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I1_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC03\;
ARCHITECTURE model OF \74HC03\ IS
BEGIN
O_A <= NOT ( A_A AND I1_A ) AFTER 2600 ps;
O_B <= NOT ( A_B AND I1_B ) AFTER 2600 ps;
O_C <= NOT ( A_C AND I1_C ) AFTER 2600 ps;
O_D <= NOT ( A_D AND I1_D ) AFTER 2600 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC03A\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I1_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC03A\;
ARCHITECTURE model OF \74HC03A\ IS
BEGIN
O_A <= NOT ( A_A AND I1_A ) AFTER 2600 ps;
O_B <= NOT ( A_B AND I1_B ) AFTER 2600 ps;
O_C <= NOT ( A_C AND I1_C ) AFTER 2600 ps;
O_D <= NOT ( A_D AND I1_D ) AFTER 2600 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC04\ IS PORT(
I_A : IN std_logic;
I_B : IN std_logic;
I_C : IN std_logic;
I_D : IN std_logic;
I_E : IN std_logic;
I_F : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
O_E : OUT std_logic;
O_F : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC04\;
ARCHITECTURE model OF \74HC04\ IS
BEGIN
O_A <= NOT ( I_A ) AFTER 1500 ps;
O_B <= NOT ( I_B ) AFTER 1500 ps;
O_C <= NOT ( I_C ) AFTER 1500 ps;
O_D <= NOT ( I_D ) AFTER 1500 ps;
O_E <= NOT ( I_E ) AFTER 1500 ps;
O_F <= NOT ( I_F ) AFTER 1500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC04A\ IS PORT(
I_A : IN std_logic;
I_B : IN std_logic;
I_C : IN std_logic;
I_D : IN std_logic;
I_E : IN std_logic;
I_F : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
O_E : OUT std_logic;
O_F : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC04A\;
ARCHITECTURE model OF \74HC04A\ IS
BEGIN
O_A <= NOT ( I_A ) AFTER 1500 ps;
O_B <= NOT ( I_B ) AFTER 1500 ps;
O_C <= NOT ( I_C ) AFTER 1500 ps;
O_D <= NOT ( I_D ) AFTER 1500 ps;
O_E <= NOT ( I_E ) AFTER 1500 ps;
O_F <= NOT ( I_F ) AFTER 1500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC05\ IS PORT(
I_A : IN std_logic;
I_B : IN std_logic;
I_C : IN std_logic;
I_D : IN std_logic;
I_E : IN std_logic;
I_F : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
O_E : OUT std_logic;
O_F : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC05\;
ARCHITECTURE model OF \74HC05\ IS
BEGIN
O_A <= NOT ( I_A ) AFTER 1900 ps;
O_B <= NOT ( I_B ) AFTER 1900 ps;
O_C <= NOT ( I_C ) AFTER 1900 ps;
O_D <= NOT ( I_D ) AFTER 1900 ps;
O_E <= NOT ( I_E ) AFTER 1900 ps;
O_F <= NOT ( I_F ) AFTER 1900 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC08\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I1_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC08\;
ARCHITECTURE model OF \74HC08\ IS
BEGIN
O_A <= ( A_A AND I1_A ) AFTER 2000 ps;
O_B <= ( A_B AND I1_B ) AFTER 2000 ps;
O_C <= ( A_C AND I1_C ) AFTER 2000 ps;
O_D <= ( A_D AND I1_D ) AFTER 2000 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC09\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I1_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC09\;
ARCHITECTURE model OF \74HC09\ IS
BEGIN
O_A <= ( A_A AND I1_A ) AFTER 2100 ps;
O_B <= ( A_B AND I1_B ) AFTER 2100 ps;
O_C <= ( A_C AND I1_C ) AFTER 2100 ps;
O_D <= ( A_D AND I1_D ) AFTER 2100 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC10\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I2_A : IN std_logic;
I2_B : IN std_logic;
I2_C : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC10\;
ARCHITECTURE model OF \74HC10\ IS
BEGIN
O_A <= NOT ( A_A AND I1_A AND I2_A ) AFTER 1500 ps;
O_B <= NOT ( A_B AND I1_B AND I2_B ) AFTER 1500 ps;
O_C <= NOT ( A_C AND I1_C AND I2_C ) AFTER 1500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC11\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
I1_A : IN std_logic;
I1_B : IN std_logic;
I1_C : IN std_logic;
I2_A : IN std_logic;
I2_B : IN std_logic;
I2_C : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC11\;
ARCHITECTURE model OF \74HC11\ IS
BEGIN
O_A <= ( A_A AND I1_A AND I2_A ) AFTER 2000 ps;
O_B <= ( A_B AND I1_B AND I2_B ) AFTER 2000 ps;
O_C <= ( A_C AND I1_C AND I2_C ) AFTER 2000 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC14\ IS PORT(
I_A : IN std_logic;
I_B : IN std_logic;
I_C : IN std_logic;
I_D : IN std_logic;
I_E : IN std_logic;
I_F : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
O_E : OUT std_logic;
O_F : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC14\;
ARCHITECTURE model OF \74HC14\ IS
BEGIN
O_A <= NOT ( I_A ) AFTER 2200 ps;
O_B <= NOT ( I_B ) AFTER 2200 ps;
O_C <= NOT ( I_C ) AFTER 2200 ps;
O_D <= NOT ( I_D ) AFTER 2200 ps;
O_E <= NOT ( I_E ) AFTER 2200 ps;
O_F <= NOT ( I_F ) AFTER 2200 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC14A\ IS PORT(
I_A : IN std_logic;
I_B : IN std_logic;
I_C : IN std_logic;
I_D : IN std_logic;
I_E : IN std_logic;
I_F : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
O_E : OUT std_logic;
O_F : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC14A\;
ARCHITECTURE model OF \74HC14A\ IS
BEGIN
O_A <= NOT ( I_A ) AFTER 2200 ps;
O_B <= NOT ( I_B ) AFTER 2200 ps;
O_C <= NOT ( I_C ) AFTER 2200 ps;
O_D <= NOT ( I_D ) AFTER 2200 ps;
O_E <= NOT ( I_E ) AFTER 2200 ps;
O_F <= NOT ( I_F ) AFTER 2200 ps;
END model;
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