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OE_B : IN std_logic;
OE_C : IN std_logic;
OE_D : IN std_logic;
GND : IN std_logic);
END \74HC126\;
ARCHITECTURE model OF \74HC126\ IS
SIGNAL N1 : std_logic;
SIGNAL N2 : std_logic;
SIGNAL N3 : std_logic;
SIGNAL N4 : std_logic;
BEGIN
N1 <= ( I_A ) AFTER 3000 ps;
N2 <= ( I_B ) AFTER 3000 ps;
N3 <= ( I_C ) AFTER 3000 ps;
N4 <= ( I_D ) AFTER 3000 ps;
TSB_8 : ORCAD_TSB
GENERIC MAP (trise_i1_o=>3000 ps, tfall_i1_o=>3000 ps, tpd_en_o=>3000 ps)
PORT MAP (O=>O_A , i1=>N1 , en=>OE_A );
TSB_9 : ORCAD_TSB
GENERIC MAP (trise_i1_o=>3000 ps, tfall_i1_o=>3000 ps, tpd_en_o=>3000 ps)
PORT MAP (O=>O_B , i1=>N2 , en=>OE_B );
TSB_10 : ORCAD_TSB
GENERIC MAP (trise_i1_o=>3000 ps, tfall_i1_o=>3000 ps, tpd_en_o=>3000 ps)
PORT MAP (O=>O_C , i1=>N3 , en=>OE_C );
TSB_11 : ORCAD_TSB
GENERIC MAP (trise_i1_o=>3000 ps, tfall_i1_o=>3000 ps, tpd_en_o=>3000 ps)
PORT MAP (O=>O_D , i1=>N4 , en=>OE_D );
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC126A\ IS PORT(
I_A : IN std_logic;
I_B : IN std_logic;
I_C : IN std_logic;
I_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
OE_A : IN std_logic;
OE_B : IN std_logic;
OE_C : IN std_logic;
OE_D : IN std_logic;
GND : IN std_logic);
END \74HC126A\;
ARCHITECTURE model OF \74HC126A\ IS
SIGNAL N1 : std_logic;
SIGNAL N2 : std_logic;
SIGNAL N3 : std_logic;
SIGNAL N4 : std_logic;
BEGIN
N1 <= ( I_A ) AFTER 3000 ps;
N2 <= ( I_B ) AFTER 3000 ps;
N3 <= ( I_C ) AFTER 3000 ps;
N4 <= ( I_D ) AFTER 3000 ps;
TSB_12 : ORCAD_TSB
GENERIC MAP (trise_i1_o=>3000 ps, tfall_i1_o=>3000 ps, tpd_en_o=>3000 ps)
PORT MAP (O=>O_A , i1=>N1 , en=>OE_A );
TSB_13 : ORCAD_TSB
GENERIC MAP (trise_i1_o=>3000 ps, tfall_i1_o=>3000 ps, tpd_en_o=>3000 ps)
PORT MAP (O=>O_B , i1=>N2 , en=>OE_B );
TSB_14 : ORCAD_TSB
GENERIC MAP (trise_i1_o=>3000 ps, tfall_i1_o=>3000 ps, tpd_en_o=>3000 ps)
PORT MAP (O=>O_C , i1=>N3 , en=>OE_C );
TSB_15 : ORCAD_TSB
GENERIC MAP (trise_i1_o=>3000 ps, tfall_i1_o=>3000 ps, tpd_en_o=>3000 ps)
PORT MAP (O=>O_D , i1=>N4 , en=>OE_D );
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC132\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
B_A : IN std_logic;
B_B : IN std_logic;
B_C : IN std_logic;
B_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC132\;
ARCHITECTURE model OF \74HC132\ IS
BEGIN
O_A <= NOT ( A_A AND B_A ) AFTER 2000 ps;
O_B <= NOT ( A_B AND B_B ) AFTER 2000 ps;
O_C <= NOT ( A_C AND B_C ) AFTER 2000 ps;
O_D <= NOT ( A_D AND B_D ) AFTER 2000 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC132A\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
A_C : IN std_logic;
A_D : IN std_logic;
B_A : IN std_logic;
B_B : IN std_logic;
B_C : IN std_logic;
B_D : IN std_logic;
O_A : OUT std_logic;
O_B : OUT std_logic;
O_C : OUT std_logic;
O_D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC132A\;
ARCHITECTURE model OF \74HC132A\ IS
BEGIN
O_A <= NOT ( A_A AND B_A ) AFTER 2000 ps;
O_B <= NOT ( A_B AND B_B ) AFTER 2000 ps;
O_C <= NOT ( A_C AND B_C ) AFTER 2000 ps;
O_D <= NOT ( A_D AND B_D ) AFTER 2000 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC133\ IS PORT(
I0 : IN std_logic;
I1 : IN std_logic;
I2 : IN std_logic;
I3 : IN std_logic;
I4 : IN std_logic;
I5 : IN std_logic;
I6 : IN std_logic;
I7 : IN std_logic;
I8 : IN std_logic;
I9 : IN std_logic;
I10 : IN std_logic;
I11 : IN std_logic;
I12 : IN std_logic;
O : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC133\;
ARCHITECTURE model OF \74HC133\ IS
BEGIN
O <= NOT ( I0 AND I1 AND I2 AND I3 AND I4 AND I5 AND I6 AND I7 AND I8 AND I9 AND I10 AND I11 AND I12 ) AFTER 3000 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC137\ IS PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
GL : IN std_logic;
G1 : IN std_logic;
G2 : IN std_logic;
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC137\;
ARCHITECTURE model OF \74HC137\ IS
SIGNAL L1 : std_logic;
SIGNAL L2 : std_logic;
SIGNAL L3 : std_logic;
SIGNAL L4 : std_logic;
SIGNAL L5 : std_logic;
SIGNAL L6 : std_logic;
SIGNAL N1 : std_logic;
SIGNAL N2 : std_logic;
SIGNAL N3 : std_logic;
BEGIN
L1 <= NOT ( G2 );
L2 <= ( L1 AND G1 );
L3 <= NOT ( GL );
DLATCH_12 : ORCAD_DLATCH
GENERIC MAP (trise_clk_q=>1200 ps, tfall_clk_q=>1200 ps)
PORT MAP (q=>N1 , d=>A , enable=>L3 );
DLATCH_13 : ORCAD_DLATCH
GENERIC MAP (trise_clk_q=>1200 ps, tfall_clk_q=>1200 ps)
PORT MAP (q=>N2 , d=>B , enable=>L3 );
DLATCH_14 : ORCAD_DLATCH
GENERIC MAP (trise_clk_q=>1200 ps, tfall_clk_q=>1200 ps)
PORT MAP (q=>N3 , d=>C , enable=>L3 );
L4 <= NOT ( N1 );
L5 <= NOT ( N2 );
L6 <= NOT ( N3 );
Y0 <= NOT ( L2 AND L4 AND L5 AND L6 ) AFTER 2600 ps;
Y1 <= NOT ( L2 AND L5 AND L6 AND N1 ) AFTER 2600 ps;
Y2 <= NOT ( L2 AND L4 AND L6 AND N2 ) AFTER 2600 ps;
Y3 <= NOT ( L2 AND L6 AND N1 AND N2 ) AFTER 2600 ps;
Y4 <= NOT ( L2 AND L4 AND L5 AND N3 ) AFTER 2600 ps;
Y5 <= NOT ( L2 AND L5 AND N1 AND N3 ) AFTER 2600 ps;
Y6 <= NOT ( L2 AND L4 AND N2 AND N3 ) AFTER 2600 ps;
Y7 <= NOT ( L2 AND N1 AND N2 AND N3 ) AFTER 2600 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC138\ IS PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
G1 : IN std_logic;
G2A : IN std_logic;
G2B : IN std_logic;
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC138\;
ARCHITECTURE model OF \74HC138\ IS
SIGNAL L1 : std_logic;
SIGNAL N1 : std_logic;
SIGNAL N2 : std_logic;
SIGNAL N3 : std_logic;
SIGNAL N4 : std_logic;
SIGNAL N5 : std_logic;
SIGNAL N6 : std_logic;
SIGNAL N7 : std_logic;
SIGNAL N8 : std_logic;
BEGIN
N1 <= ( A ) AFTER 3000 ps;
N2 <= ( B ) AFTER 3000 ps;
N3 <= ( C ) AFTER 3000 ps;
N4 <= NOT ( A ) AFTER 3000 ps;
N5 <= NOT ( B ) AFTER 3000 ps;
N6 <= NOT ( C ) AFTER 3000 ps;
N7 <= ( G1 ) AFTER 2000 ps;
N8 <= NOT ( G2A OR G2B ) AFTER 2500 ps;
L1 <= ( N7 AND N8 );
Y0 <= NOT ( L1 AND N4 AND N5 AND N6 ) AFTER 500 ps;
Y1 <= NOT ( L1 AND N1 AND N5 AND N6 ) AFTER 500 ps;
Y2 <= NOT ( L1 AND N2 AND N4 AND N6 ) AFTER 500 ps;
Y3 <= NOT ( L1 AND N1 AND N2 AND N6 ) AFTER 500 ps;
Y4 <= NOT ( L1 AND N3 AND N4 AND N5 ) AFTER 500 ps;
Y5 <= NOT ( L1 AND N1 AND N3 AND N5 ) AFTER 500 ps;
Y6 <= NOT ( L1 AND N2 AND N3 AND N4 ) AFTER 500 ps;
Y7 <= NOT ( L1 AND N1 AND N2 AND N3 ) AFTER 500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC138A\ IS PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
G1 : IN std_logic;
G2A : IN std_logic;
G2B : IN std_logic;
Y0 : OUT std_logic;
Y1 : OUT std_logic;
Y2 : OUT std_logic;
Y3 : OUT std_logic;
Y4 : OUT std_logic;
Y5 : OUT std_logic;
Y6 : OUT std_logic;
Y7 : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC138A\;
ARCHITECTURE model OF \74HC138A\ IS
SIGNAL L1 : std_logic;
SIGNAL N1 : std_logic;
SIGNAL N2 : std_logic;
SIGNAL N3 : std_logic;
SIGNAL N4 : std_logic;
SIGNAL N5 : std_logic;
SIGNAL N6 : std_logic;
SIGNAL N7 : std_logic;
SIGNAL N8 : std_logic;
BEGIN
N1 <= ( A ) AFTER 3000 ps;
N2 <= ( B ) AFTER 3000 ps;
N3 <= ( C ) AFTER 3000 ps;
N4 <= NOT ( A ) AFTER 3000 ps;
N5 <= NOT ( B ) AFTER 3000 ps;
N6 <= NOT ( C ) AFTER 3000 ps;
N7 <= ( G1 ) AFTER 2000 ps;
N8 <= NOT ( G2A OR G2B ) AFTER 2500 ps;
L1 <= ( N7 AND N8 );
Y0 <= NOT ( L1 AND N4 AND N5 AND N6 ) AFTER 500 ps;
Y1 <= NOT ( L1 AND N1 AND N5 AND N6 ) AFTER 500 ps;
Y2 <= NOT ( L1 AND N2 AND N4 AND N6 ) AFTER 500 ps;
Y3 <= NOT ( L1 AND N1 AND N2 AND N6 ) AFTER 500 ps;
Y4 <= NOT ( L1 AND N3 AND N4 AND N5 ) AFTER 500 ps;
Y5 <= NOT ( L1 AND N1 AND N3 AND N5 ) AFTER 500 ps;
Y6 <= NOT ( L1 AND N2 AND N3 AND N4 ) AFTER 500 ps;
Y7 <= NOT ( L1 AND N1 AND N2 AND N3 ) AFTER 500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC139\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
B_A : IN std_logic;
B_B : IN std_logic;
G_A : IN std_logic;
G_B : IN std_logic;
Y0_A : OUT std_logic;
Y0_B : OUT std_logic;
Y1_A : OUT std_logic;
Y1_B : OUT std_logic;
Y2_A : OUT std_logic;
Y2_B : OUT std_logic;
Y3_A : OUT std_logic;
Y3_B : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC139\;
ARCHITECTURE model OF \74HC139\ IS
SIGNAL N1 : std_logic;
SIGNAL N2 : std_logic;
SIGNAL N3 : std_logic;
SIGNAL N4 : std_logic;
SIGNAL N5 : std_logic;
SIGNAL N6 : std_logic;
SIGNAL N7 : std_logic;
SIGNAL N8 : std_logic;
SIGNAL N9 : std_logic;
SIGNAL N10 : std_logic;
BEGIN
N1 <= NOT ( G_A ) AFTER 2500 ps;
N2 <= ( A_A ) AFTER 3300 ps;
N3 <= ( B_A ) AFTER 3300 ps;
N4 <= NOT ( A_A ) AFTER 2500 ps;
N5 <= NOT ( B_A ) AFTER 2500 ps;
N6 <= NOT ( G_B ) AFTER 2500 ps;
N7 <= ( A_B ) AFTER 3300 ps;
N8 <= ( B_B ) AFTER 3300 ps;
N9 <= NOT ( A_B ) AFTER 2500 ps;
N10 <= NOT ( B_B ) AFTER 2500 ps;
Y0_A <= NOT ( N1 AND N4 AND N5 ) AFTER 500 ps;
Y1_A <= NOT ( N1 AND N2 AND N5 ) AFTER 500 ps;
Y2_A <= NOT ( N1 AND N3 AND N4 ) AFTER 500 ps;
Y3_A <= NOT ( N1 AND N2 AND N3 ) AFTER 500 ps;
Y0_B <= NOT ( N6 AND N9 AND N10 ) AFTER 500 ps;
Y1_B <= NOT ( N6 AND N7 AND N10 ) AFTER 500 ps;
Y2_B <= NOT ( N6 AND N8 AND N9 ) AFTER 500 ps;
Y3_B <= NOT ( N6 AND N7 AND N8 ) AFTER 500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC139A\ IS PORT(
A_A : IN std_logic;
A_B : IN std_logic;
B_A : IN std_logic;
B_B : IN std_logic;
G_A : IN std_logic;
G_B : IN std_logic;
Y0_A : OUT std_logic;
Y0_B : OUT std_logic;
Y1_A : OUT std_logic;
Y1_B : OUT std_logic;
Y2_A : OUT std_logic;
Y2_B : OUT std_logic;
Y3_A : OUT std_logic;
Y3_B : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC139A\;
ARCHITECTURE model OF \74HC139A\ IS
SIGNAL N1 : std_logic;
SIGNAL N2 : std_logic;
SIGNAL N3 : std_logic;
SIGNAL N4 : std_logic;
SIGNAL N5 : std_logic;
SIGNAL N6 : std_logic;
SIGNAL N7 : std_logic;
SIGNAL N8 : std_logic;
SIGNAL N9 : std_logic;
SIGNAL N10 : std_logic;
BEGIN
N1 <= NOT ( G_A ) AFTER 2500 ps;
N2 <= ( A_A ) AFTER 3300 ps;
N3 <= ( B_A ) AFTER 3300 ps;
N4 <= NOT ( A_A ) AFTER 2500 ps;
N5 <= NOT ( B_A ) AFTER 2500 ps;
N6 <= NOT ( G_B ) AFTER 2500 ps;
N7 <= ( A_B ) AFTER 3300 ps;
N8 <= ( B_B ) AFTER 3300 ps;
N9 <= NOT ( A_B ) AFTER 2500 ps;
N10 <= NOT ( B_B ) AFTER 2500 ps;
Y0_A <= NOT ( N1 AND N4 AND N5 ) AFTER 500 ps;
Y1_A <= NOT ( N1 AND N2 AND N5 ) AFTER 500 ps;
Y2_A <= NOT ( N1 AND N3 AND N4 ) AFTER 500 ps;
Y3_A <= NOT ( N1 AND N2 AND N3 ) AFTER 500 ps;
Y0_B <= NOT ( N6 AND N9 AND N10 ) AFTER 500 ps;
Y1_B <= NOT ( N6 AND N7 AND N10 ) AFTER 500 ps;
Y2_B <= NOT ( N6 AND N8 AND N9 ) AFTER 500 ps;
Y3_B <= NOT ( N6 AND N7 AND N8 ) AFTER 500 ps;
END model;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.orcad_prims.all;
ENTITY \74HC147\ IS PORT(
\1\ : IN std_logic;
\2\ : IN std_logic;
\3\ : IN std_logic;
\4\ : IN std_logic;
\5\ : IN std_logic;
\6\ : IN std_logic;
\7\ : IN std_logic;
\8\ : IN std_logic;
\9\ : IN std_logic;
A : OUT std_logic;
B : OUT std_logic;
C : OUT std_logic;
D : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic);
END \74HC147\;
ARCHITECTURE model OF \74HC147\ IS
SIGNAL L1 : std_logic;
SIGNAL L2 : std_logic;
SIGNAL L3 : std_logic;
SIGNAL L4 : std_logic;
SIGNAL L5 : std_logic;
SIGNAL L6 : std_logic;
SIGNAL L7 : std_logic;
SIGNAL L8 : std_logic;
SIGNAL L9 : std_logic;
SIGNAL L10 : std_logic;
SIGNAL L11 : std_logic;
SIGNAL L12 : std_logic;
SIGNAL L13 : std_logic;
SIGNAL L14 : std_logic;
SIGNAL L15 : std_logic;
SIGNAL L16 : std_logic;
SIGNAL L17 : std_logic;
SIGNAL L18 : std_logic;
BEGIN
L1 <= NOT ( \1\ );
L2 <= NOT ( \2\ );
L3 <= NOT ( \3\ );
L4 <= NOT ( \4\ );
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