?? adderful.map.summary
字號:
Analysis & Synthesis Status : Successful - Thu May 17 19:53:46 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : adderful
Top-level Entity Name : adderful
Family : Cyclone
Total logic elements : 32
Total pins : 67
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -