library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32b is
  port( clk:in std_logic;
        wp:in std_logic_vector(1 downto 0);
        a: in std_logic_vector(31 downto 0);
        b: buffer std_logic_vector(31 downto 0)
      );
end adder32b;
architecture rets of adder32b is
signal reset :std_logic:='0';
signal s:std_logic_vector(31 downto 0);
begin
  p1:process(clk,reset)
     variable m,n,k,f,g,h:std_logic_vector(31 downto 0);
    begin
      m:=(others=>'0');
      n:="00111111110000000000000000000000";
      g:="01000000000000000000000000000000";
      k:="01111111110000000000000000000000";
      h:="10000000000000000000000000000000";
      f:="10111111110000000000000000000000";
      if reset='1' then
         s<=(others=>'0');
      elsif clk'event and clk='1' then
         case wp is
             when "00" =>
                         if s>n then
                         s<=m;
                         else
                         s<=a+b; end if;
                         b<=s;
             when "01" =>
                         if s>k then
                         s<=g;
                         else
                         s<=a+b; end if;
                         b<=s;
             when "10" =>
                         if s>f then                        
                         s<=h;
                         else
                         s<=a+b; end if;
                         b<=s;
             when others=> null;
        end case;
    end if;
  end process p1;
p2:process(wp)
   variable m:std_logic;
   begin
     m:='1';
   reset<=(wp(0) or wp(1)) or m;
  end process p2;
end rets;