{ "Info" "ITDB_TSU_RESULT" "s\[1\] p\[1\] clk 5.010 ns register " "Info: tsu for register \"s\[1\]\" (data pin = \"p\[1\]\", clock pin = \"clk\") is 5.010 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.143 ns + Longest pin register " "Info: + Longest pin to register delay is 8.143 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns p\[1\] 1 PIN PIN_215 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_215; Fanout = 1; PIN Node = 'p\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { p[1] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.359 ns) + CELL(0.309 ns) 8.143 ns s\[1\] 2 REG LC_X16_Y11_N2 1 " "Info: 2: + IC(6.359 ns) + CELL(0.309 ns) = 8.143 ns; Loc. = LC_X16_Y11_N2; Fanout = 1; REG Node = 's\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.668 ns" { p[1] s[1] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns ( 21.91 % ) " "Info: Total cell delay = 1.784 ns ( 21.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.359 ns ( 78.09 % ) " "Info: Total interconnect delay = 6.359 ns ( 78.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.143 ns" { p[1] s[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.143 ns" { p[1] p[1]~out0 s[1] } { 0.000ns 0.000ns 6.359ns } { 0.000ns 1.475ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.170 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns s\[1\] 2 REG LC_X16_Y11_N2 1 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X16_Y11_N2; Fanout = 1; REG Node = 's\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clk s[1] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk s[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 s[1] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.143 ns" { p[1] s[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.143 ns" { p[1] p[1]~out0 s[1] } { 0.000ns 0.000ns 6.359ns } { 0.000ns 1.475ns 0.309ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk s[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 s[1] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[1\] s\[1\] 7.804 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[1\]\" through register \"s\[1\]\" is 7.804 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.170 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.170 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.711 ns) 3.170 ns s\[1\] 2 REG LC_X16_Y11_N2 1 " "Info: 2: + IC(0.990 ns) + CELL(0.711 ns) = 3.170 ns; Loc. = LC_X16_Y11_N2; Fanout = 1; REG Node = 's\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.701 ns" { clk s[1] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.77 % ) " "Info: Total cell delay = 2.180 ns ( 68.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.990 ns ( 31.23 % ) " "Info: Total interconnect delay = 0.990 ns ( 31.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk s[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 s[1] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.410 ns + Longest register pin " "Info: + Longest register to pin delay is 4.410 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns s\[1\] 1 REG LC_X16_Y11_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y11_N2; Fanout = 1; REG Node = 's\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { s[1] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.302 ns) + CELL(2.108 ns) 4.410 ns q\[1\] 2 PIN PIN_86 0 " "Info: 2: + IC(2.302 ns) + CELL(2.108 ns) = 4.410 ns; Loc. = PIN_86; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.410 ns" { s[1] q[1] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 47.80 % ) " "Info: Total cell delay = 2.108 ns ( 47.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.302 ns ( 52.20 % ) " "Info: Total interconnect delay = 2.302 ns ( 52.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.410 ns" { s[1] q[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.410 ns" { s[1] q[1] } { 0.000ns 2.302ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.170 ns" { clk s[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.170 ns" { clk clk~out0 s[1] } { 0.000ns 0.000ns 0.990ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.410 ns" { s[1] q[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.410 ns" { s[1] q[1] } { 0.000ns 2.302ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "s\[11\] p\[11\] clk -2.886 ns register " "Info: th for register \"s\[11\]\" (data pin = \"p\[11\]\", clock pin = \"clk\") is -2.886 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.246 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.066 ns) + CELL(0.711 ns) 3.246 ns s\[11\] 2 REG LC_X1_Y22_N2 1 " "Info: 2: + IC(1.066 ns) + CELL(0.711 ns) = 3.246 ns; Loc. = LC_X1_Y22_N2; Fanout = 1; REG Node = 's\[11\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.777 ns" { clk s[11] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.16 % ) " "Info: Total cell delay = 2.180 ns ( 67.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.066 ns ( 32.84 % ) " "Info: Total interconnect delay = 1.066 ns ( 32.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.246 ns" { clk s[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.246 ns" { clk clk~out0 s[11] } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.147 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns p\[11\] 1 PIN PIN_15 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_15; Fanout = 1; PIN Node = 'p\[11\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { p[11] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.563 ns) + CELL(0.115 ns) 6.147 ns s\[11\] 2 REG LC_X1_Y22_N2 1 " "Info: 2: + IC(4.563 ns) + CELL(0.115 ns) = 6.147 ns; Loc. = LC_X1_Y22_N2; Fanout = 1; REG Node = 's\[11\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.678 ns" { p[11] s[11] } "NODE_NAME" } } { "adderful.vhd" "" { Text "D:/altera/quartus60/program/DDS/adderful.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 25.77 % ) " "Info: Total cell delay = 1.584 ns ( 25.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.563 ns ( 74.23 % ) " "Info: Total interconnect delay = 4.563 ns ( 74.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.147 ns" { p[11] s[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.147 ns" { p[11] p[11]~out0 s[11] } { 0.000ns 0.000ns 4.563ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.246 ns" { clk s[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.246 ns" { clk clk~out0 s[11] } { 0.000ns 0.000ns 1.066ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.147 ns" { p[11] s[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.147 ns" { p[11] p[11]~out0 s[11] } { 0.000ns 0.000ns 4.563ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 19:54:13 2007 " "Info: Processing ended: Thu May 17 19:54:13 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}