Analysis & Synthesis report for ddsok
Thu May 17 22:49:56 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (Restructuring Performed)
 11. Source assignments for data_rom:u2|altsyncram:altsyncram_component|altsyncram_cs41:auto_generated|altsyncram_ani2:altsyncram1
 12. Source assignments for data_rom:u2|altsyncram:altsyncram_component|altsyncram_cs41:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 13. Source assignments for sld_signaltap:cnts
 14. Source assignments for sld_signaltap:cnts|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_dmi2:auto_generated
 15. Source assignments for sld_signaltap:cnts|sld_rom_sr:crc_rom_sr
 16. Source assignments for sld_hub:sld_hub_inst
 17. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 18. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 19. Parameter Settings for User Entity Instance: data_rom:u2|altsyncram:altsyncram_component
 20. Parameter Settings for User Entity Instance: data_rom:u2|altsyncram:altsyncram_component|altsyncram_cs41:auto_generated|sld_mod_ram_rom:mgl_prim2
 21. Parameter Settings for Inferred Entity Instance: sld_signaltap:cnts
 22. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 23. SignalTap II Logic Analyzer Settings
 24. In-System Memory Content Editor Settings
 25. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu May 17 22:49:56 2007    ;
; Quartus II Version          ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name               ; ddsok                                    ;
; Top-level Entity Name       ; ddsok                                    ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 536                                      ;
; Total pins                  ; 23                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 24,576                                   ;