|vgainterface
reset => count_y[3].ACLR
reset => count_y[2].ACLR
reset => count_y[1].ACLR
reset => count_y[0].ACLR
reset => vga_h_sync.ACLR
reset => vga_v_sync.ACLR
reset => vga_read.ACLR
reset => vga_green.ACLR
reset => vga_blue.ACLR
reset => vga_blue_dispaly~reg0.ACLR
reset => vga_hs_control~reg0.ACLR
reset => vga_vs_control~reg0.ACLR
reset => vga_read_dispaly~reg0.ACLR
reset => vga_green_dispaly~reg0.ACLR
reset => address[0].ACLR
reset => address[1].ACLR
reset => address[2].ACLR
reset => address[3].ACLR
reset => address[4].ACLR
reset => address[5].ACLR
reset => address[6].ACLR
reset => address[7].ACLR
reset => address[8].ACLR
reset => address[9].ACLR
reset => address[10].ACLR
reset => address[11].ACLR
reset => address[12].ACLR
reset => address[13].ACLR
reset => count_y[4].ACLR
reset => count_y[5].ACLR
reset => count_y[6].ACLR
reset => count_y[7].ACLR
reset => count_y[8].ACLR
reset => count_x[0].ACLR
reset => count_x[1].ACLR
reset => count_x[2].ACLR
reset => count_x[3].ACLR
reset => count_x[4].ACLR
reset => count_x[5].ACLR
reset => count_x[6].ACLR
reset => count_x[7].ACLR
reset => count_x[8].ACLR
reset => count_x[9].ACLR
reset => clock_25mhz.ACLR
reset => count_z[0].ACLR
reset => count_z[1].ACLR
reset => count_z[2].ACLR
reset => count_z[3].ACLR
reset => count_z[4].ACLR
clock0 => tsinghua:u1.inclock
clock0 => clock_25mhz.CLK
clock2 => count_z[0].CLK
clock2 => count_z[1].CLK
clock2 => count_z[2].CLK
clock2 => count_z[3].CLK
clock2 => count_z[4].CLK
vga_hs_control <= vga_hs_control~reg0.DB_MAX_OUTPUT_PORT_TYPE
vga_vs_control <= vga_vs_control~reg0.DB_MAX_OUTPUT_PORT_TYPE
vga_read_dispaly <= vga_read_dispaly~reg0.DB_MAX_OUTPUT_PORT_TYPE
vga_green_dispaly <= vga_green_dispaly~reg0.DB_MAX_OUTPUT_PORT_TYPE
vga_blue_dispaly <= vga_blue_dispaly~reg0.DB_MAX_OUTPUT_PORT_TYPE


|vgainterface|tsinghua:u1
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
address[8] => altsyncram:altsyncram_component.address_a[8]
address[9] => altsyncram:altsyncram_component.address_a[9]
address[10] => altsyncram:altsyncram_component.address_a[10]
address[11] => altsyncram:altsyncram_component.address_a[11]
address[12] => altsyncram:altsyncram_component.address_a[12]
address[13] => altsyncram:altsyncram_component.address_a[13]
inclock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]


|vgainterface|tsinghua:u1|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_6h41:auto_generated.address_a[0]
address_a[1] => altsyncram_6h41:auto_generated.address_a[1]
address_a[2] => altsyncram_6h41:auto_generated.address_a[2]
address_a[3] => altsyncram_6h41:auto_generated.address_a[3]
address_a[4] => altsyncram_6h41:auto_generated.address_a[4]
address_a[5] => altsyncram_6h41:auto_generated.address_a[5]
address_a[6] => altsyncram_6h41:auto_generated.address_a[6]
address_a[7] => altsyncram_6h41:auto_generated.address_a[7]
address_a[8] => altsyncram_6h41:auto_generated.address_a[8]
address_a[9] => altsyncram_6h41:auto_generated.address_a[9]
address_a[10] => altsyncram_6h41:auto_generated.address_a[10]
address_a[11] => altsyncram_6h41:auto_generated.address_a[11]
address_a[12] => altsyncram_6h41:auto_generated.address_a[12]
address_a[13] => altsyncram_6h41:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_6h41:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_6h41:auto_generated.q_a[0]
q_b[0] <= <GND>


|vgainterface|tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[12] => decode_iga:deep_decode.data[0]
address_a[13] => address_reg_a[1].DATAIN
address_a[13] => decode_iga:deep_decode.data[1]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
q_a[0] <= mux_rab:mux2.result[0]


|vgainterface|tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated|decode_iga:deep_decode
data[0] => w_anode42w[1].IN1
data[0] => w_anode58w[1].IN1
data[1] => w_anode50w[2].IN1
data[1] => w_anode58w[2].IN1
enable => w_anode29w[1].IN0
enable => w_anode42w[1].IN0
enable => w_anode50w[1].IN0
enable => w_anode58w[1].IN0
eq[0] <= w_anode29w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode42w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode50w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode58w[2].DB_MAX_OUTPUT_PORT_TYPE


|vgainterface|tsinghua:u1|altsyncram:altsyncram_component|altsyncram_6h41:auto_generated|mux_rab:mux2
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE