// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
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//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
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// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
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//   consistency and functionality through the use of formal
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//   regarding the use or functionality of this code.
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// Revision History :
//---------------------------------------------------------------------
// Ver  | Author    | Mod. Date | Changes Made:
//---------------------------------------------------------------------
// 0.1  | tpf       | 11/23/98  | birth
// 1.0  | tpf       |  3/19/98  | Release
//---------------------------------------------------------------------

`timescale 1 ns /  100 ps

/*
This is the signal module for the synchronous DRAM controller.  It 
monitors the output of the state machine vectors and outputs the 
appropriate signals at the right time.
*/

module sd_sig(  add,
                wr_l,
                byte_en,
                term_l,
                sdram_cycle,
                state_cntr,
                sdram_mode_reg,
                sdram_cmnd,
                rst_l,                 
                clk,
                sd_add,
                sd_ba,
                sd_cs0_l,
                sd_cs1_l,
                sd_ras_l,
                sd_cas_l,
                sd_we_l,
                sd_cke,
                sd_dqm,
                ack_l);

//---------------------------------------------------------------------
// inputs

input  [24:0]	add;
input           wr_l;
input  [3:0]    byte_en;
input           term_l;
input  [3:0]    sdram_cycle;
input  [3:0]    state_cntr;
input  [11:0]   sdram_mode_reg;
input  [1:0]    sdram_cmnd;
input           rst_l;           
input           clk;
     
//---------------------------------------------------------------------
// outputs     
     
output [11:0]   sd_add;
output [1:0]    sd_ba;
output          sd_cs0_l;
output          sd_cs1_l;
output          sd_ras_l;
output          sd_cas_l;
output          sd_we_l;
output          sd_cke;
output [3:0]    sd_dqm;
output          ack_l;
				
//---------------------------------------------------------------------
// registers

reg    [11:0]   sd_add;
reg    [1:0]    sd_ba;
reg             sd_cs0_l;
reg             sd_cs1_l;
reg             sd_ras_l;
reg             sd_cas_l;
reg             sd_we_l;
reg             sd_cke;
reg    [3:0]    sd_dqm;
reg             ack_l;
reg             term_lcatch;
reg             term_ldly;
				
//---------------------------------------------------------------------
// equations

// this is for 32 bit wide array
// address bits 0-1 are not used

always @(posedge clk or negedge rst_l)
   if (!rst_l)
        sd_add <= #1 12'h400;                           // precharge
   else if (sdram_cycle[1] && (state_cntr == 4'b0) 
                           && (sdram_cmnd == 2'b11))
        sd_add <= #1 sdram_mode_reg;
   else if (sdram_cycle[2] && (state_cntr == 4'b0000))  // ras time
        sd_add <= #1 add[21:10];
   else if (sdram_cycle[2] && (state_cntr == 4'b0010))  // cas time
        sd_add <= #1 {4'hf,add[9:2]};
   else
        sd_add <= #1 12'h400;                           // precharge

// bank addresses
always @(posedge clk or negedge rst_l)
   if (!rst_l)
        sd_ba <= #1 2'b00;
   else if (sdram_cycle[2] && (state_cntr == 4'b0000))  // ras time
        sd_ba <= #1 add[23:22];
   else if (sdram_cycle[2] && (state_cntr == 4'b0010))  // cas time
        sd_ba <= #1 add[23:22];
   else
        sd_ba <= #1 2'b00;

// chip select 0
always @(posedge clk or negedge rst_l)
   if (!rst_l)
        sd_cs0_l <= #1 1'b1;
   else if (sdram_cycle[1] && (state_cntr == 4'b0000))  // cmd cycle
        sd_cs0_l <= #1 1'b0;
   else if (sdram_cycle[2] && (state_cntr == 4'b0000))  // ras time
        sd_cs0_l <=  #1 add[24];
   else if (sdram_cycle[2] && (state_cntr == 4'b0010))  // cas time
        sd_cs0_l <= #1 add[24];
   else if (sdram_cycle[3] &&
    (state_cntr == 4'b0000))                            // refresh time
        sd_cs0_l <= #1 1'b0;
   else if (term_lcatch && sdram_cycle[2] && !add[24])   // term cycle
        sd_cs0_l <= #1 1'b0;
   else
        sd_cs0_l <= #1 1'b1;

// chip select 1
always @(posedge clk or negedge rst_l)
   if (!rst_l)
        sd_cs1_l <= #1 1'b1;
   else if (sdram_cycle[1] && (state_cntr == 4'b0000))  // cmd cycle
        sd_cs1_l <= #1 1'b0;
   else if (sdram_cycle[2] && (state_cntr == 4'b0000))  // ras time
        sd_cs1_l <=  #1 ~add[24];
   else if (sdram_cycle[2] && (state_cntr == 4'b0010))  // cas time
        sd_cs1_l <= #1 ~add[24];
   else if (sdram_cycle[3] && (state_cntr == 4'b0000))  // refresh time
        sd_cs1_l <= #1 1'b0;
   else if (term_lcatch && sdram_cycle[2] && add[24])    // term cycle
        sd_cs1_l <= #1 1'b0;
   else
        sd_cs1_l <= #1 1'b1;

// ras
always @(posedge clk or negedge rst_l)
   if (!rst_l)      
        sd_ras_l <= #1 1'b1;
   else if ((sdram_cycle[1] && (state_cntr == 4'b0000))  // cmd cycle
      ||    (sdram_cycle[2] && (state_cntr == 4'b0000))  // ras time
      ||    (sdram_cycle[3] && (state_cntr == 4'b0000))) // refresh time
        sd_ras_l <= #1 1'b0;
   else
        sd_ras_l <= #1 1'b1;

// cas
always @(posedge clk or negedge rst_l)
   if (!rst_l)      
        sd_cas_l <= #1 1'b1;
   else if ((sdram_cycle[1] && (state_cntr == 4'b0) && sdram_cmnd[1])
      ||    (sdram_cycle[2] && (state_cntr == 4'b0010)) // cas time
      ||    (sdram_cycle[3] && (state_cntr == 4'b0000)))// refresh time
          sd_cas_l <= #1 1'b0;
   else
          sd_cas_l <= #1 1'b1;

// we
always @(posedge clk or negedge rst_l)
   if (!rst_l)      
        sd_we_l <= #1 1'b1;
   else if ((sdram_cycle[1] && (state_cntr == 4'b0) 
                            && sdram_cmnd[0])           // cmd cycle
      ||    (sdram_cycle[2] && (state_cntr == 4'b0010)
                            && !wr_l)                   // cas time
      ||    (sdram_cycle[2] && term_lcatch))             // terminate
        sd_we_l <= #1 1'b0;
   else
        sd_we_l <= #1 1'b1;

// clock enable
always @(posedge clk or negedge rst_l)      
   if (!rst_l)
        sd_cke <= #1 1'b0;
   else
        sd_cke <= #1 1'b1;
      
// data mask
always @(posedge clk or negedge rst_l)
   if (!rst_l)            
        sd_dqm <= #1 4'b0;
   else if (sdram_cycle[2] && (state_cntr  == 4'b0010))
        sd_dqm <= #1 byte_en;     
   else if (state_cntr == 4'b1010)                  // burst = 8
        sd_dqm <= #1 4'b0;
      
// acknowledge
always @(posedge clk or negedge rst_l)
   if (!rst_l)
        ack_l <= #1 1'b1;
   else if (sdram_cycle[2] && (state_cntr == 4'b0010) && !wr_l)
        ack_l <= #1 1'b0;      
// for cas latency 2 use state_cntr == 4'b0011
// for cas latency 3 use state_cntr == 4'b0100
   else if (sdram_cycle[2] && (state_cntr == 4'b0011) &&  wr_l) 
        ack_l <= #1 1'b0;
   else if ((state_cntr == 4'b1010) && !wr_l)
        ack_l <= #1 1'b1;
// change for burst size other than 8
// for cas latency 2 use state_cntr == 4'b1011
// for cas latency 3 use state_cntr == 4'b1100
   else if ((state_cntr == 4'b1011) &&  wr_l)
        ack_l <=  #1 1'b1;
// if the cycle terminates        
   else if (!sdram_cycle[2])    
      
        ack_l <= #1 1'b1;

// terminate catch -- only want 1 tick wide pulse
        
always @(posedge clk or negedge rst_l)
    if (!rst_l) 
        term_ldly   <= #1 1'b0;
    else 
        term_ldly   <= #1 ~term_l;   

always @(posedge clk or negedge rst_l)
    if (!rst_l) 
        term_lcatch <= #1 1'b0;
    else if (!term_l && !term_ldly)
        term_lcatch <= #1 1'b1;
    else
        term_lcatch <= #1 1'b0;    
      
endmodule