// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
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//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
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// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
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//   consistency and functionality through the use of formal
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// Revision History :
//---------------------------------------------------------------------
// Ver  | Author    | Mod. Date | Changes Made:
//---------------------------------------------------------------------
// 0.1  | tpf       | 11/23/98  | birth
// 1.0  | tpf       |  3/19/99  | Release
//---------------------------------------------------------------------

`timescale 1 ns /  100 ps

/*
This is the refresh module for the synchronous DRAM controller.  It 
includes a 12 bit counter which counts clock ticks.  The counter 
provides a refresh request every 15.8 usec.  Select the right parameter
based on the input clock frequency
*/

module sd_rfrsh(  clk,
                  rst_l,
                  sdram_setup,
                  sdram_cycle,
                  rfrsh_req);
                  
//---------------------------------------------------------------------
// port list

input          	clk;
input          	rst_l;
input          	sdram_setup;
input  [3:0]   	sdram_cycle;

output         	rfrsh_req;

//---------------------------------------------------------------------
// registers

reg            	rfrsh_req;

reg   [10:0]   	rfrsh_cntr;

//---------------------------------------------------------------------
// parameters -- set count to desired clock frequency

parameter cnt_66 = 1053;               // 66 Mhz clock
parameter cnt_50 = 790;                // 50 Mhz clock
parameter cnt_40 = 632;                // 40 Mhz clock
parameter cnt_33 = 526;                // 33 Mhz clock
parameter count = cnt_66;              // set for 66 mhz

//---------------------------------------------------------------------
// refresh counter 

always @(posedge clk or negedge rst_l)
   if (!rst_l)
      rfrsh_cntr <= #1 11'b0;
   else if (sdram_setup && rfrsh_cntr != count)
      rfrsh_cntr <= #1 rfrsh_cntr + 1; 
   else
      rfrsh_cntr <= #1 11'b0;
   
//---------------------------------------------------------------------
// refresh request 

always @(posedge clk or negedge rst_l)
   if (!rst_l)
      rfrsh_req <= #1 1'b0;
   else if (rfrsh_cntr == count)       
      rfrsh_req <= #1 1'b1;             
   else if (sdram_cycle[3])
      rfrsh_req <= #1 1'b0;

endmodule