// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
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// Revision History :
//---------------------------------------------------------------------
// Ver  | Author    | Mod. Date | Changes Made:
//---------------------------------------------------------------------
// 0.1  | tpf       | 11/23/98  | birth
// 1.0  | tpf       |  3/19/99  | Release
//---------------------------------------------------------------------

`timescale 1 ns /  100 ps

/*
This is the top level module for a synchronous DRAM controller.  It 
includes a register value, a state machine, and a signal output module.
*/

module sd_top( 	sdram_cs_l,         // sdram select
				wr_l,               // write strobe
				sdram_en,			// sdram enable
				term_l,              // cycle terminate
				clk,                // sdram clock
				rst_l,              // reset signal
				byte_en,            // byte enables
				add,                // address bus
				sd_cke,             // sdram clock enable
				sd_ba,              // sdram bank address
				sd_cs0_l,           // sdram chip select 0
               	sd_cs1_l,           // sdram chip select 1
				sd_ras_l,           // sdram row address
				sd_cas_l,           // sdram column select
				sd_we_l,            // sdram write enable
				sd_add,             // sdram address
				sd_dqm,             // sdram data qual mask
				ack_l,              // sdram cycle acknowledge
                sdram_setup);       // sdram setup completed
				
//---------------------------------------------------------------------
// inputs

input          	sdram_cs_l;
input          	wr_l;
input			sdram_en;
input          	term_l;
input          	clk;
input          	rst_l;
input  [3:0]   	byte_en;
input  [24:0]  	add;

//---------------------------------------------------------------------
// outputs

output         	sd_cke;
output [1:0]   	sd_ba;
output         	sd_cs0_l,
               	sd_cs1_l,
               	sd_ras_l,
				sd_cas_l,
				sd_we_l;
output [11:0]  	sd_add;
output [3:0]   	sd_dqm;              // change width for data width
output         	ack_l;               // 
output          sdram_setup;

//---------------------------------------------------------------------
// intermodule wires

wire   [11:0]  	sdram_mode_reg;
wire   [1:0]   	sdram_cmnd;
wire   [3:0]   	sdram_cycle;         // type of cycle
wire   [3:0]   	state_cntr;          // command cycle bits
wire           	rfrsh_req;           // refresh clock

//---------------------------------------------------------------------
// modules


sd_cnfg U1 (   	.sdram_en(sdram_en),
				.clk(clk),
               	.rst_l(rst_l),
               	.sdram_cycle(sdram_cycle),
                .state_cntr(state_cntr),
               	.sdram_mode_reg(sdram_mode_reg),
               	.sdram_cmnd(sdram_cmnd),
               	.cmnd_cycle_req(cmnd_cycle_req),
               	.sdram_setup(sdram_setup));
                                 
sd_state U2(   	.sdram_cs_l(sdram_cs_l),
               	.cmnd_cycle_req(cmnd_cycle_req),
               	.rfrsh_req(rfrsh_req),
               	.clk(clk),
               	.rst_l(rst_l),
               	.sdram_cycle(sdram_cycle),
               	.state_cntr(state_cntr));
			   	
sd_rfrsh U3(   	.clk(clk),
               	.rst_l(rst_l),
               	.sdram_setup(sdram_setup),
               	.sdram_cycle(sdram_cycle),
               	.rfrsh_req(rfrsh_req));
                  
sd_sig U4(     	.add(add),
               	.wr_l(wr_l),
               	.byte_en(byte_en),
               	.term_l(term_l),
               	.sdram_cycle(sdram_cycle),
               	.state_cntr(state_cntr),
               	.sdram_mode_reg(sdram_mode_reg),
               	.sdram_cmnd(sdram_cmnd),
               	.rst_l(rst_l),                 
               	.clk(clk),
               	.sd_add(sd_add),
               	.sd_ba(sd_ba),
               	.sd_cs0_l(sd_cs0_l),
               	.sd_cs1_l(sd_cs1_l),
               	.sd_ras_l(sd_ras_l),
               	.sd_cas_l(sd_cas_l),
               	.sd_we_l(sd_we_l),
               	.sd_cke(sd_cke),
               	.sd_dqm(sd_dqm),
               	.ack_l(ack_l));
               	   
endmodule