// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Copyright (c) 2001 by Lattice Semiconductor Corporation
// --------------------------------------------------------------------
//
// Permission:
//
//   Lattice Semiconductor grants permission to use this code for use
//   in synthesis for any Lattice programmable logic product.  Other
//   use of this code, including the selling or duplication of any
//   portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL or Verilog source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Lattice Semiconductor provides no warranty
//   regarding the use or functionality of this code.
//
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//                     Lattice Semiconductor Corporation
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// Revision History :
//---------------------------------------------------------------------
// Ver  | Author    | Mod. Date | Changes Made:
//---------------------------------------------------------------------
// 0.1  | tpf       | 11/23/98  | birth
// 1.0  | tpf       |  3/19/99  | Release
//--------------------------------------------------------------------


`timescale 1 ns /  100 ps

/*
This is the state machine for the synchronous DRAM controller.  It 
outputs 2 binary encoded vectors one indicates the kind of
sdram cycle requested and the second indicates the state.
*/

module sd_state(sdram_cs_l,
                cmnd_cycle_req,
                rfrsh_req,
                clk,
                rst_l,
                sdram_cycle,
                state_cntr);

//--------------------------------------------------------------------
// inputs

input           sdram_cs_l;
input           cmnd_cycle_req;
input           rfrsh_req;
input           clk;
input           rst_l;

//--------------------------------------------------------------------
// outputs
                  
output [3:0]    sdram_cycle;
output [3:0]    state_cntr;
				
//--------------------------------------------------------------------
// registers

reg    [3:0]    sdram_cycle;
reg    [3:0]    state_cntr;
				
//--------------------------------------------------------------------
// state parameters

parameter idl_cycle = 4'b0001;
parameter cmd_cycle = 4'b0010;
parameter dat_cycle = 4'b0100;
parameter rfr_cycle = 4'b1000;

//--------------------------------------------------------------------
// state machine

always @(posedge clk or negedge rst_l)

   if (!rst_l)
      sdram_cycle <= #1 idl_cycle;

   else case (sdram_cycle)
      
      idl_cycle : if (cmnd_cycle_req)
                     sdram_cycle <= #1 cmd_cycle;
                  else if (!sdram_cs_l)
                     sdram_cycle <= #1 dat_cycle;
                  else if (rfrsh_req)
                     sdram_cycle <= #1 rfr_cycle;
                  else
                     sdram_cycle <= #1 idl_cycle;
                     
      cmd_cycle : if (state_cntr[3])
                     sdram_cycle <= #1 idl_cycle;
                     
      dat_cycle : if (sdram_cs_l)
                     sdram_cycle <= #1 idl_cycle;
                     
      rfr_cycle : if (state_cntr == 4'hc)
                     sdram_cycle <= #1 idl_cycle;
                     
      default   :    sdram_cycle <= #1 4'bx;

      endcase
      
//--------------------------------------------------------------------
// command cycle counter      

always @(posedge clk or negedge rst_l)
   if (!rst_l)
      state_cntr <= #1 4'b0;
   else if (!sdram_cycle[0])
      state_cntr <= #1 state_cntr + 1;
   else
      state_cntr <= #1 4'b0;
      

endmodule