?? up3_clock.sim.rpt
字號:
; |UP3_CLOCK|Select~3720 ; |UP3_CLOCK|Select~3720 ; combout ;
; |UP3_CLOCK|Select~3721 ; |UP3_CLOCK|Select~3721 ; combout ;
; |UP3_CLOCK|Select~3722 ; |UP3_CLOCK|Select~3722 ; combout ;
; |UP3_CLOCK|Select~3723 ; |UP3_CLOCK|Select~3723 ; combout ;
; |UP3_CLOCK|Select~3724 ; |UP3_CLOCK|Select~3724 ; combout ;
; |UP3_CLOCK|Select~3726 ; |UP3_CLOCK|Select~3726 ; combout ;
; |UP3_CLOCK|Select~3727 ; |UP3_CLOCK|Select~3727 ; combout ;
; |UP3_CLOCK|Select~3728 ; |UP3_CLOCK|Select~3728 ; combout ;
; |UP3_CLOCK|BCD_DAY0[3] ; |UP3_CLOCK|BCD_DAY0[3] ; regout ;
; |UP3_CLOCK|Select~3729 ; |UP3_CLOCK|Select~3729 ; combout ;
; |UP3_CLOCK|Select~3730 ; |UP3_CLOCK|Select~3730 ; combout ;
; |UP3_CLOCK|Select~3731 ; |UP3_CLOCK|Select~3731 ; combout ;
; |UP3_CLOCK|Select~3732 ; |UP3_CLOCK|Select~3732 ; combout ;
; |UP3_CLOCK|Select~3733 ; |UP3_CLOCK|Select~3733 ; combout ;
; |UP3_CLOCK|state.write_display_char9~43 ; |UP3_CLOCK|state.write_display_char9~43 ; combout ;
; |UP3_CLOCK|next_command.write_display_char10 ; |UP3_CLOCK|next_command.write_display_char10 ; regout ;
; |UP3_CLOCK|next_command.write_char18 ; |UP3_CLOCK|next_command.write_char18 ; regout ;
; |UP3_CLOCK|next_command.write_char10 ; |UP3_CLOCK|next_command.write_char10 ; regout ;
; |UP3_CLOCK|CLK_COUNT_400HZ[3] ; |UP3_CLOCK|CLK_COUNT_400HZ[3]~416 ; cout0 ;
; |UP3_CLOCK|CLK_COUNT_400HZ[3] ; |UP3_CLOCK|CLK_COUNT_400HZ[3]~416COUT1_435 ; cout1 ;
; |UP3_CLOCK|next_command.write_char5 ; |UP3_CLOCK|next_command.write_char5 ; regout ;
; |UP3_CLOCK|next_command.write_display_char4 ; |UP3_CLOCK|next_command.write_display_char4 ; regout ;
; |UP3_CLOCK|BCD_DAY0[0]~7 ; |UP3_CLOCK|BCD_DAY0[0]~7 ; combout ;
; |UP3_CLOCK|next_command.write_char7 ; |UP3_CLOCK|next_command.write_char7 ; regout ;
; |UP3_CLOCK|next_command.write_display_char2 ; |UP3_CLOCK|next_command.write_display_char2 ; regout ;
; |UP3_CLOCK|next_command.write_char2 ; |UP3_CLOCK|next_command.write_char2 ; regout ;
; |UP3_CLOCK|next_command.write_display_char1 ; |UP3_CLOCK|next_command.write_display_char1 ; regout ;
; |UP3_CLOCK|next_command.write_char8 ; |UP3_CLOCK|next_command.write_char8 ; regout ;
; |UP3_CLOCK|next_command.write_char13 ; |UP3_CLOCK|next_command.write_char13 ; regout ;
; |UP3_CLOCK|next_command.write_char16 ; |UP3_CLOCK|next_command.write_char16 ; regout ;
; |UP3_CLOCK|next_command.write_char4 ; |UP3_CLOCK|next_command.write_char4 ; regout ;
; |UP3_CLOCK|next_command.write_display_char5 ; |UP3_CLOCK|next_command.write_display_char5 ; regout ;
; |UP3_CLOCK|next_command.write_display_char7 ; |UP3_CLOCK|next_command.write_display_char7 ; regout ;
; |UP3_CLOCK|next_command.write_display_char8 ; |UP3_CLOCK|next_command.write_display_char8 ; regout ;
; |UP3_CLOCK|next_command.write_char1 ; |UP3_CLOCK|next_command.write_char1 ; regout ;
; |UP3_CLOCK|next_command.write_char3 ; |UP3_CLOCK|next_command.write_char3 ; regout ;
; |UP3_CLOCK|next_command.write_char6 ; |UP3_CLOCK|next_command.write_char6 ; regout ;
; |UP3_CLOCK|next_command.write_display_char3 ; |UP3_CLOCK|next_command.write_display_char3 ; regout ;
; |UP3_CLOCK|next_command.write_display_char6 ; |UP3_CLOCK|next_command.write_display_char6 ; regout ;
; |UP3_CLOCK|next_command.write_char9 ; |UP3_CLOCK|next_command.write_char9 ; regout ;
; |UP3_CLOCK|next_command.write_display_char9 ; |UP3_CLOCK|next_command.write_display_char9 ; regout ;
; |UP3_CLOCK|state.write_char17 ; |UP3_CLOCK|state.write_char17 ; regout ;
; |UP3_CLOCK|CLK_COUNT_400HZ[2] ; |UP3_CLOCK|CLK_COUNT_400HZ[2]~420 ; cout0 ;
; |UP3_CLOCK|CLK_COUNT_400HZ[2] ; |UP3_CLOCK|CLK_COUNT_400HZ[2]~420COUT1_434 ; cout1 ;
; |UP3_CLOCK|Select~3747 ; |UP3_CLOCK|Select~3747 ; combout ;
; |UP3_CLOCK|state.write_char12 ; |UP3_CLOCK|state.write_char12 ; regout ;
; |UP3_CLOCK|state.write_char15 ; |UP3_CLOCK|state.write_char15 ; regout ;
; |UP3_CLOCK|next_command.write_char17 ; |UP3_CLOCK|next_command.write_char17 ; regout ;
; |UP3_CLOCK|CLK_COUNT_400HZ[1] ; |UP3_CLOCK|CLK_COUNT_400HZ[1]~424 ; cout0 ;
; |UP3_CLOCK|CLK_COUNT_400HZ[1] ; |UP3_CLOCK|CLK_COUNT_400HZ[1]~424COUT1_433 ; cout1 ;
; |UP3_CLOCK|next_command.write_char12 ; |UP3_CLOCK|next_command.write_char12 ; regout ;
; |UP3_CLOCK|next_command.write_char15 ; |UP3_CLOCK|next_command.write_char15 ; regout ;
; |UP3_CLOCK|CLK_COUNT_400HZ[0] ; |UP3_CLOCK|CLK_COUNT_400HZ[0]~428 ; cout0 ;
; |UP3_CLOCK|CLK_COUNT_400HZ[0] ; |UP3_CLOCK|CLK_COUNT_400HZ[0]~428COUT1_432 ; cout1 ;
; |UP3_CLOCK|state.write_char11 ; |UP3_CLOCK|state.write_char11 ; regout ;
; |UP3_CLOCK|state.write_char14 ; |UP3_CLOCK|state.write_char14 ; regout ;
; |UP3_CLOCK|next_command.write_char11 ; |UP3_CLOCK|next_command.write_char11 ; regout ;
; |UP3_CLOCK|next_command.write_char14 ; |UP3_CLOCK|next_command.write_char14 ; regout ;
; |UP3_CLOCK|ALARM_LED~166 ; |UP3_CLOCK|ALARM_LED~166 ; combout ;
; |UP3_CLOCK|BCD_S1[3]~282 ; |UP3_CLOCK|BCD_S1[3]~282 ; combout ;
; |UP3_CLOCK|BCD_M0[3]~289 ; |UP3_CLOCK|BCD_M0[3]~289 ; combout ;
; |UP3_CLOCK|state1~241 ; |UP3_CLOCK|state1~241 ; combout ;
; |UP3_CLOCK|state2~226 ; |UP3_CLOCK|state2~226 ; combout ;
; |UP3_CLOCK|reset ; |UP3_CLOCK|reset ; combout ;
; |UP3_CLOCK|CLOSE_ALARM ; |UP3_CLOCK|CLOSE_ALARM ; combout ;
; |UP3_CLOCK|SET_ALARM ; |UP3_CLOCK|SET_ALARM ; combout ;
; |UP3_CLOCK|GIVE_TIME ; |UP3_CLOCK|GIVE_TIME ; combout ;
; |UP3_CLOCK|SET_MOD ; |UP3_CLOCK|SET_MOD ; combout ;
; |UP3_CLOCK|SET_CHANGE ; |UP3_CLOCK|SET_CHANGE ; combout ;
; |UP3_CLOCK|SET_TIME ; |UP3_CLOCK|SET_TIME ; combout ;
; |UP3_CLOCK|SET_ADD ; |UP3_CLOCK|SET_ADD ; combout ;
; |UP3_CLOCK|clk_48Mhz ; |UP3_CLOCK|clk_48Mhz ; combout ;
; |UP3_CLOCK|ALARM ; |UP3_CLOCK|ALARM ; combout ;
; |UP3_CLOCK|LCD_RS ; |UP3_CLOCK|LCD_RS ; padio ;
; |UP3_CLOCK|LCD_E ; |UP3_CLOCK|LCD_E ; padio ;
; |UP3_CLOCK|RESET_LED ; |UP3_CLOCK|RESET_LED ; padio ;
; |UP3_CLOCK|SEC_LED ; |UP3_CLOCK|SEC_LED ; padio ;
; |UP3_CLOCK|ALARM_LED ; |UP3_CLOCK|ALARM_LED ; padio ;
; |UP3_CLOCK|GIVE_TIME_LED ; |UP3_CLOCK|GIVE_TIME_LED ; padio ;
; |UP3_CLOCK|LCD_RW ; |UP3_CLOCK|LCD_RW ; padio ;
; |UP3_CLOCK|DATA_BUS[0]~output ; |UP3_CLOCK|DATA_BUS[0]~output ; padio ;
; |UP3_CLOCK|DATA_BUS[1]~output ; |UP3_CLOCK|DATA_BUS[1]~output ; padio ;
; |UP3_CLOCK|DATA_BUS[2]~output ; |UP3_CLOCK|DATA_BUS[2]~output ; padio ;
; |UP3_CLOCK|DATA_BUS[3]~output ; |UP3_CLOCK|DATA_BUS[3]~output ; padio ;
; |UP3_CLOCK|DATA_BUS[4]~output ; |UP3_CLOCK|DATA_BUS[4]~output ; padio ;
; |UP3_CLOCK|DATA_BUS[5]~output ; |UP3_CLOCK|DATA_BUS[5]~output ; padio ;
; |UP3_CLOCK|DATA_BUS[6]~output ; |UP3_CLOCK|DATA_BUS[6]~output ; padio ;
; |UP3_CLOCK|DATA_BUS[7]~output ; |UP3_CLOCK|DATA_BUS[7]~output ; padio ;
+----------------------------------------------+----------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+----------------------------------------------+----------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+----------------------------------------------+----------------------------------------------+------------------+
; |UP3_CLOCK|BCD_SECD0[2] ; |UP3_CLOCK|BCD_SECD0[2] ; regout ;
; |UP3_CLOCK|BCD_S0[0] ; |UP3_CLOCK|BCD_S0[0] ; regout ;
; |UP3_CLOCK|process3~354 ; |UP3_CLOCK|process3~354 ; combout ;
; |UP3_CLOCK|BCD_SECD0[1] ; |UP3_CLOCK|BCD_SECD0[1] ; regout ;
; |UP3_CLOCK|BCD_S0[1] ; |UP3_CLOCK|BCD_S0[1] ; regout ;
; |UP3_CLOCK|BCD_SECD0[3] ; |UP3_CLOCK|BCD_SECD0[3] ; regout ;
; |UP3_CLOCK|BCD_S0[3] ; |UP3_CLOCK|BCD_S0[3] ; regout ;
; |UP3_CLOCK|Equal~329 ; |UP3_CLOCK|Equal~329 ; combout ;
; |UP3_CLOCK|process3~355 ; |UP3_CLOCK|process3~355 ; combout ;
; |UP3_CLOCK|process3~356 ; |UP3_CLOCK|process3~356 ; combout ;
; |UP3_CLOCK|BCD_MIND1[2] ; |UP3_CLOCK|BCD_MIND1[2] ; regout ;
; |UP3_CLOCK|BCD_M1[1] ; |UP3_CLOCK|BCD_M1[1] ; regout ;
; |UP3_CLOCK|process3~357 ; |UP3_CLOCK|process3~357 ; combout ;
; |UP3_CLOCK|BCD_MIND1[0] ; |UP3_CLOCK|BCD_MIND1[0] ; regout ;
; |UP3_CLOCK|BCD_M1[0] ; |UP3_CLOCK|BCD_M1[0] ; regout ;
; |UP3_CLOCK|BCD_H1[0] ; |UP3_CLOCK|BCD_H1[0] ; regout ;
; |UP3_CLOCK|process3~358 ; |UP3_CLOCK|process3~358 ; combout ;
; |UP3_CLOCK|process3~359 ; |UP3_CLOCK|process3~359 ; combout ;
; |UP3_CLOCK|BCD_MIND0[2] ; |UP3_CLOCK|BCD_MIND0[2] ; regout ;
; |UP3_CLOCK|BCD_M0[2] ; |UP3_CLOCK|BCD_M0[2] ; regout ;
; |UP3_CLOCK|process3~360 ; |UP3_CLOCK|process3~360 ; combout ;
; |UP3_CLOCK|BCD_MIND0[0] ; |UP3_CLOCK|BCD_MIND0[0] ; regout ;
; |UP3_CLOCK|BCD_M0[0] ; |UP3_CLOCK|BCD_M0[0] ; regout ;
; |UP3_CLOCK|process3~361 ; |UP3_CLOCK|process3~361 ; combout ;
; |UP3_CLOCK|process3~362 ; |UP3_CLOCK|process3~362 ; combout ;
; |UP3_CLOCK|BCD_S1[0] ; |UP3_CLOCK|BCD_S1[0] ; regout ;
; |UP3_CLOCK|BCD_MIND0[1] ; |UP3_CLOCK|BCD_MIND0[1] ; regout ;
; |UP3_CLOCK|BCD_M0[1] ; |UP3_CLOCK|BCD_M0[1] ?? 快捷鍵說明
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