{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jun 09 21:40:58 2007 " "Info: Processing started: Sat Jun 09 21:40:58 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off UP3_CLOCK -c UP3_CLOCK " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off UP3_CLOCK -c UP3_CLOCK" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "UP3_CLOCK EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"UP3_CLOCK\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk_48Mhz Global clock in PIN 29 " "Info: Automatically promoted signal \"clk_48Mhz\" to use Global clock in PIN 29" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "CLK_400HZ Global clock " "Info: Automatically promoted some destinations of signal \"CLK_400HZ\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_400HZ " "Info: Destination \"CLK_400HZ\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "CLK_10HZ Global clock " "Info: Automatically promoted some destinations of signal \"CLK_10HZ\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_10HZ " "Info: Destination \"CLK_10HZ\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "RESET_LED " "Info: Destination \"RESET_LED\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 9 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_400HZ " "Info: Destination \"CLK_400HZ\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_10HZ " "Info: Destination \"CLK_10HZ\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_COUNT_10HZ\[6\] " "Info: Destination \"CLK_COUNT_10HZ\[6\]\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_COUNT_10HZ\[7\] " "Info: Destination \"CLK_COUNT_10HZ\[7\]\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_COUNT_10HZ\[0\] " "Info: Destination \"CLK_COUNT_10HZ\[0\]\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_COUNT_10HZ\[1\] " "Info: Destination \"CLK_COUNT_10HZ\[1\]\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_COUNT_10HZ\[2\] " "Info: Destination \"CLK_COUNT_10HZ\[2\]\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_COUNT_10HZ\[3\] " "Info: Destination \"CLK_COUNT_10HZ\[3\]\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "CLK_COUNT_10HZ\[4\] " "Info: Destination \"CLK_COUNT_10HZ\[4\]\" may be non-global or may not use global clock" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}