{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_10HZ " "Info: Detected ripple clock \"CLK_10HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_10HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_400HZ " "Info: Detected ripple clock \"CLK_400HZ\" as buffer" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK_400HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_48Mhz register BCD_SECD1\[2\] register DATA_BUS_VALUE\[2\] 94.42 MHz 10.591 ns Internal " "Info: Clock \"clk_48Mhz\" has Internal fmax of 94.42 MHz between source register \"BCD_SECD1\[2\]\" and destination register \"DATA_BUS_VALUE\[2\]\" (period= 10.591 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.857 ns + Longest register register " "Info: + Longest register to register delay is 5.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_SECD1\[2\] 1 REG LC_X20_Y10_N6 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y10_N6; Fanout = 8; REG Node = 'BCD_SECD1\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "" { BCD_SECD1[2] } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 419 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.232 ns) + CELL(0.590 ns) 2.822 ns Select~3718 2 COMB LC_X15_Y9_N2 1 " "Info: 2: + IC(2.232 ns) + CELL(0.590 ns) = 2.822 ns; Loc. = LC_X15_Y9_N2; Fanout = 1; COMB Node = 'Select~3718'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "2.822 ns" { BCD_SECD1[2] Select~3718 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.453 ns) + CELL(0.590 ns) 3.865 ns Select~3720 3 COMB LC_X15_Y9_N4 1 " "Info: 3: + IC(0.453 ns) + CELL(0.590 ns) = 3.865 ns; Loc. = LC_X15_Y9_N4; Fanout = 1; COMB Node = 'Select~3720'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "1.043 ns" { Select~3718 Select~3720 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.738 ns) 5.857 ns DATA_BUS_VALUE\[2\] 4 REG LC_X19_Y9_N7 2 " "Info: 4: + IC(1.254 ns) + CELL(0.738 ns) = 5.857 ns; Loc. = LC_X19_Y9_N7; Fanout = 2; REG Node = 'DATA_BUS_VALUE\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "1.992 ns" { Select~3720 DATA_BUS_VALUE[2] } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.918 ns ( 32.75 % ) " "Info: Total cell delay = 1.918 ns ( 32.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.939 ns ( 67.25 % ) " "Info: Total interconnect delay = 3.939 ns ( 67.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "5.857 ns" { BCD_SECD1[2] Select~3718 Select~3720 DATA_BUS_VALUE[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.857 ns" { BCD_SECD1[2] Select~3718 Select~3720 DATA_BUS_VALUE[2] } { 0.000ns 2.232ns 0.453ns 1.254ns } { 0.000ns 0.590ns 0.590ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.473 ns - Smallest " "Info: - Smallest clock skew is -4.473 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 8.991 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_48Mhz\" to destination register is 8.991 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'clk_48Mhz'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "" { clk_48Mhz } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns CLK_400HZ 2 REG LC_X20_Y16_N9 99 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X20_Y16_N9; Fanout = 99; REG Node = 'CLK_400HZ'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "1.717 ns" { clk_48Mhz CLK_400HZ } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.094 ns) + CELL(0.711 ns) 8.991 ns DATA_BUS_VALUE\[2\] 3 REG LC_X19_Y9_N7 2 " "Info: 3: + IC(5.094 ns) + CELL(0.711 ns) = 8.991 ns; Loc. = LC_X19_Y9_N7; Fanout = 2; REG Node = 'DATA_BUS_VALUE\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "5.805 ns" { CLK_400HZ DATA_BUS_VALUE[2] } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 34.65 % ) " "Info: Total cell delay = 3.115 ns ( 34.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.876 ns ( 65.35 % ) " "Info: Total interconnect delay = 5.876 ns ( 65.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "8.991 ns" { clk_48Mhz CLK_400HZ DATA_BUS_VALUE[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.991 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ DATA_BUS_VALUE[2] } { 0.000ns 0.000ns 0.782ns 5.094ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz source 13.464 ns - Longest register " "Info: - Longest clock path from clock \"clk_48Mhz\" to source register is 13.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'clk_48Mhz'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "" { clk_48Mhz } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns CLK_400HZ 2 REG LC_X20_Y16_N9 99 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X20_Y16_N9; Fanout = 99; REG Node = 'CLK_400HZ'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "1.717 ns" { clk_48Mhz CLK_400HZ } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.105 ns) + CELL(0.935 ns) 9.226 ns CLK_10HZ 3 REG LC_X8_Y10_N2 69 " "Info: 3: + IC(5.105 ns) + CELL(0.935 ns) = 9.226 ns; Loc. = LC_X8_Y10_N2; Fanout = 69; REG Node = 'CLK_10HZ'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "6.040 ns" { CLK_400HZ CLK_10HZ } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.527 ns) + CELL(0.711 ns) 13.464 ns BCD_SECD1\[2\] 4 REG LC_X20_Y10_N6 8 " "Info: 4: + IC(3.527 ns) + CELL(0.711 ns) = 13.464 ns; Loc. = LC_X20_Y10_N6; Fanout = 8; REG Node = 'BCD_SECD1\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "4.238 ns" { CLK_10HZ BCD_SECD1[2] } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 419 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 30.08 % ) " "Info: Total cell delay = 4.050 ns ( 30.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.414 ns ( 69.92 % ) " "Info: Total interconnect delay = 9.414 ns ( 69.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "13.464 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_SECD1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.464 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_SECD1[2] } { 0.000ns 0.000ns 0.782ns 5.105ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "8.991 ns" { clk_48Mhz CLK_400HZ DATA_BUS_VALUE[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.991 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ DATA_BUS_VALUE[2] } { 0.000ns 0.000ns 0.782ns 5.094ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "13.464 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_SECD1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.464 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_SECD1[2] } { 0.000ns 0.000ns 0.782ns 5.105ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 419 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 67 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "5.857 ns" { BCD_SECD1[2] Select~3718 Select~3720 DATA_BUS_VALUE[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.857 ns" { BCD_SECD1[2] Select~3718 Select~3720 DATA_BUS_VALUE[2] } { 0.000ns 2.232ns 0.453ns 1.254ns } { 0.000ns 0.590ns 0.590ns 0.738ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "8.991 ns" { clk_48Mhz CLK_400HZ DATA_BUS_VALUE[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.991 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ DATA_BUS_VALUE[2] } { 0.000ns 0.000ns 0.782ns 5.094ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學習/EDA技術應用/EDA/實驗三－電子表/最終版本/project1_clock/" "" "13.464 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_SECD1[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.464 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_SECD1[2] } { 0.000ns 0.000ns 0.782ns 5.105ns 3.527ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}