{ "Info" "ITDB_TSU_RESULT" "CLK_COUNT_400HZ\[18\] reset clk_48Mhz 8.389 ns register " "Info: tsu for register \"CLK_COUNT_400HZ\[18\]\" (data pin = \"reset\", clock pin = \"clk_48Mhz\") is 8.389 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.314 ns + Longest pin register " "Info: + Longest pin to register delay is 11.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns reset 1 PIN PIN_23 166 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 166; PIN Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { reset } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.199 ns) + CELL(0.292 ns) 8.960 ns CLK_COUNT_400HZ\[13\]~410 2 COMB LC_X20_Y16_N6 20 " "Info: 2: + IC(7.199 ns) + CELL(0.292 ns) = 8.960 ns; Loc. = LC_X20_Y16_N6; Fanout = 20; COMB Node = 'CLK_COUNT_400HZ\[13\]~410'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "7.491 ns" { reset CLK_COUNT_400HZ[13]~410 } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(1.112 ns) 11.314 ns CLK_COUNT_400HZ\[18\] 3 REG LC_X21_Y15_N8 5 " "Info: 3: + IC(1.242 ns) + CELL(1.112 ns) = 11.314 ns; Loc. = LC_X21_Y15_N8; Fanout = 5; REG Node = 'CLK_COUNT_400HZ\[18\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "2.354 ns" { CLK_COUNT_400HZ[13]~410 CLK_COUNT_400HZ[18] } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.873 ns ( 25.39 % ) " "Info: Total cell delay = 2.873 ns ( 25.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.441 ns ( 74.61 % ) " "Info: Total interconnect delay = 8.441 ns ( 74.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "11.314 ns" { reset CLK_COUNT_400HZ[13]~410 CLK_COUNT_400HZ[18] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.314 ns" { reset reset~out0 CLK_COUNT_400HZ[13]~410 CLK_COUNT_400HZ[18] } { 0.000ns 0.000ns 7.199ns 1.242ns } { 0.000ns 1.469ns 0.292ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 61 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_48Mhz\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'clk_48Mhz'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { clk_48Mhz } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns CLK_COUNT_400HZ\[18\] 2 REG LC_X21_Y15_N8 5 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X21_Y15_N8; Fanout = 5; REG Node = 'CLK_COUNT_400HZ\[18\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "1.493 ns" { clk_48Mhz CLK_COUNT_400HZ[18] } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "2.962 ns" { clk_48Mhz CLK_COUNT_400HZ[18] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk_48Mhz clk_48Mhz~out0 CLK_COUNT_400HZ[18] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "11.314 ns" { reset CLK_COUNT_400HZ[13]~410 CLK_COUNT_400HZ[18] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.314 ns" { reset reset~out0 CLK_COUNT_400HZ[13]~410 CLK_COUNT_400HZ[18] } { 0.000ns 0.000ns 7.199ns 1.242ns } { 0.000ns 1.469ns 0.292ns 1.112ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "2.962 ns" { clk_48Mhz CLK_COUNT_400HZ[18] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.962 ns" { clk_48Mhz clk_48Mhz~out0 CLK_COUNT_400HZ[18] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_48Mhz ALARM_LED BCD_MIND0\[2\] 51.523 ns register " "Info: tco from clock \"clk_48Mhz\" to destination pin \"ALARM_LED\" through register \"BCD_MIND0\[2\]\" is 51.523 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_48Mhz source 13.435 ns + Longest register " "Info: + Longest clock path from clock \"clk_48Mhz\" to source register is 13.435 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_48Mhz 1 CLK PIN_29 21 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 21; CLK Node = 'clk_48Mhz'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { clk_48Mhz } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns CLK_400HZ 2 REG LC_X20_Y16_N9 99 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X20_Y16_N9; Fanout = 99; REG Node = 'CLK_400HZ'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "1.717 ns" { clk_48Mhz CLK_400HZ } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.105 ns) + CELL(0.935 ns) 9.226 ns CLK_10HZ 3 REG LC_X8_Y10_N2 69 " "Info: 3: + IC(5.105 ns) + CELL(0.935 ns) = 9.226 ns; Loc. = LC_X8_Y10_N2; Fanout = 69; REG Node = 'CLK_10HZ'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "6.040 ns" { CLK_400HZ CLK_10HZ } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.498 ns) + CELL(0.711 ns) 13.435 ns BCD_MIND0\[2\] 4 REG LC_X20_Y8_N1 7 " "Info: 4: + IC(3.498 ns) + CELL(0.711 ns) = 13.435 ns; Loc. = LC_X20_Y8_N1; Fanout = 7; REG Node = 'BCD_MIND0\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "4.209 ns" { CLK_10HZ BCD_MIND0[2] } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 419 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 30.15 % ) " "Info: Total cell delay = 4.050 ns ( 30.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.385 ns ( 69.85 % ) " "Info: Total interconnect delay = 9.385 ns ( 69.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "13.435 ns" { clk_48Mhz CLK_400HZ CLK_10HZ BCD_MIND0[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.435 ns" { clk_48Mhz clk_48Mhz~out0 CLK_400HZ CLK_10HZ BCD_MIND0[2] } { 0.000ns 0.000ns 0.782ns 5.105ns 3.498ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 419 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "37.864 ns + Longest register pin " "Info: + Longest register to pin delay is 37.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns BCD_MIND0\[2\] 1 REG LC_X20_Y8_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y8_N1; Fanout = 7; REG Node = 'BCD_MIND0\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { BCD_MIND0[2] } "NODE_NAME" } "" } } { "UP3_CLOCK.vhd" "" { Text "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/UP3_CLOCK.vhd" 419 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.093 ns) + CELL(0.442 ns) 2.535 ns process3~360 2 COMB LC_X16_Y9_N5 1 " "Info: 2: + IC(2.093 ns) + CELL(0.442 ns) = 2.535 ns; Loc. = LC_X16_Y9_N5; Fanout = 1; COMB Node = 'process3~360'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "2.535 ns" { BCD_MIND0[2] process3~360 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.211 ns) + CELL(0.442 ns) 4.188 ns process3~362 3 COMB LC_X16_Y8_N1 1 " "Info: 3: + IC(1.211 ns) + CELL(0.442 ns) = 4.188 ns; Loc. = LC_X16_Y8_N1; Fanout = 1; COMB Node = 'process3~362'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "1.653 ns" { process3~360 process3~362 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.048 ns) + CELL(0.114 ns) 6.350 ns process3~367 4 COMB LC_X21_Y11_N8 1 " "Info: 4: + IC(2.048 ns) + CELL(0.114 ns) = 6.350 ns; Loc. = LC_X21_Y11_N8; Fanout = 1; COMB Node = 'process3~367'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "2.162 ns" { process3~362 process3~367 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.007 ns) + CELL(0.114 ns) 8.471 ns process3~368 5 COMB LC_X14_Y10_N8 34 " "Info: 5: + IC(2.007 ns) + CELL(0.114 ns) = 8.471 ns; Loc. = LC_X14_Y10_N8; Fanout = 34; COMB Node = 'process3~368'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "2.121 ns" { process3~367 process3~368 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(23.003 ns) 31.474 ns process3~369 6 COMB LOOP LC_X14_Y10_N2 2 " "Info: 6: + IC(0.000 ns) + CELL(23.003 ns) = 31.474 ns; Loc. = LC_X14_Y10_N2; Fanout = 2; COMB LOOP Node = 'process3~369'" { { "Info" "ITDB_PART_OF_SCC" "add~3314 LC_X15_Y14_N4 " "Info: Loc. = LC_X15_Y14_N4; Node \"add~3314\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3314 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3346 LC_X15_Y15_N9 " "Info: Loc. = LC_X15_Y15_N9; Node \"add~3346\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3346 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3322 LC_X15_Y14_N3 " "Info: Loc. = LC_X15_Y14_N3; Node \"add~3322\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3322 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3322COUT1_3530 LC_X15_Y14_N3 " "Info: Loc. = LC_X15_Y14_N3; Node \"add~3322COUT1_3530\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3322COUT1_3530 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3316 LC_X15_Y14_N4 " "Info: Loc. = LC_X15_Y14_N4; Node \"add~3316\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3316 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3344 LC_X15_Y15_N9 " "Info: Loc. = LC_X15_Y15_N9; Node \"add~3344\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3344 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3376 LC_X15_Y15_N4 " "Info: Loc. = LC_X15_Y15_N4; Node \"add~3376\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3376 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3352 LC_X15_Y15_N8 " "Info: Loc. = LC_X15_Y15_N8; Node \"add~3352\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3352 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3352COUT1_3526 LC_X15_Y15_N8 " "Info: Loc. = LC_X15_Y15_N8; Node \"add~3352COUT1_3526\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3352COUT1_3526 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3320 LC_X15_Y14_N3 " "Info: Loc. = LC_X15_Y14_N3; Node \"add~3320\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3320 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3328 LC_X15_Y14_N2 " "Info: Loc. = LC_X15_Y14_N2; Node \"add~3328\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3328 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3328COUT1_3529 LC_X15_Y14_N2 " "Info: Loc. = LC_X15_Y14_N2; Node \"add~3328COUT1_3529\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3328COUT1_3529 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3326 LC_X15_Y14_N2 " "Info: Loc. = LC_X15_Y14_N2; Node \"add~3326\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3326 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3334 LC_X15_Y14_N1 " "Info: Loc. = LC_X15_Y14_N1; Node \"add~3334\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3334 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3334COUT1_3528 LC_X15_Y14_N1 " "Info: Loc. = LC_X15_Y14_N1; Node \"add~3334COUT1_3528\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3334COUT1_3528 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3332 LC_X15_Y14_N1 " "Info: Loc. = LC_X15_Y14_N1; Node \"add~3332\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3332 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3340 LC_X15_Y14_N0 " "Info: Loc. = LC_X15_Y14_N0; Node \"add~3340\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3340 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3340COUT1_3527 LC_X15_Y14_N0 " "Info: Loc. = LC_X15_Y14_N0; Node \"add~3340COUT1_3527\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3340COUT1_3527 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3338 LC_X15_Y14_N0 " "Info: Loc. = LC_X15_Y14_N0; Node \"add~3338\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3338 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3374 LC_X15_Y15_N4 " "Info: Loc. = LC_X15_Y15_N4; Node \"add~3374\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3374 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3406 LC_X15_Y16_N9 " "Info: Loc. = LC_X15_Y16_N9; Node \"add~3406\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3406 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3382 LC_X15_Y15_N3 " "Info: Loc. = LC_X15_Y15_N3; Node \"add~3382\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/db/UP3_CLOCK.quartus_db" { Floorplan "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_clock/" "" "" { add~3382 } "NODE_NAME" } "" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "add~3382COUT1_3522 LC_X15_Y15_N3 " "Info: Loc. = LC_X15_Y15_N3; Node \"add~3382COUT1_3522\"" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "UP3_CLOCK" "UNKNOWN" "V1" "H:/學(xué)習(xí)/EDA技術(shù)應(yīng)用/EDA/實(shí)驗(yàn)三－電子表/最終版本/project1_cloc