PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
areset
clk
clk
clk
clk
clk
clk
inclk
inclk
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|stratix_pll.inc
1107575584
c:|altera|quartus50|libraries|megafunctions|stratixii_pll.inc
1107575806
c:|altera|quartus50|libraries|megafunctions|cycloneii_pll.inc
1107575944
}
# hierarchies {
VGA_Audio_PLL:p1|altpll:altpll_component
}
# end
# entity
SEG7_LUT_8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT_8.v
1124911122
7
# storage
db|DE2_Default.(4).cnf
db|DE2_Default.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SEG7_LUT_8:u0
}
# end
# entity
SEG7_LUT
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT.v
1126850200
7
# storage
db|DE2_Default.(5).cnf
db|DE2_Default.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SEG7_LUT_8:u0|SEG7_LUT:u0
SEG7_LUT_8:u0|SEG7_LUT:u1
SEG7_LUT_8:u0|SEG7_LUT:u2
SEG7_LUT_8:u0|SEG7_LUT:u3
SEG7_LUT_8:u0|SEG7_LUT:u4
SEG7_LUT_8:u0|SEG7_LUT:u5
SEG7_LUT_8:u0|SEG7_LUT:u6
SEG7_LUT_8:u0|SEG7_LUT:u7
}
# end
# entity
VGA_Controller
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_Controller|VGA_Controller.v
1134223460
7
# storage
db|DE2_Default.(6).cnf
db|DE2_Default.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
H_SYNC_CYC
96
PARAMETER_DEC
DEF
H_SYNC_BACK
48
PARAMETER_DEC
DEF
H_SYNC_ACT
640
PARAMETER_DEC
DEF
H_SYNC_FRONT
16
PARAMETER_DEC
DEF
H_SYNC_TOTAL
800
PARAMETER_DEC
DEF
V_SYNC_CYC
2
PARAMETER_DEC
DEF
V_SYNC_BACK
32
PARAMETER_DEC
DEF
V_SYNC_ACT
480
PARAMETER_DEC
DEF
V_SYNC_FRONT
11
PARAMETER_DEC
DEF
V_SYNC_TOTAL
525
PARAMETER_DEC
DEF
X_START
148
PARAMETER_DEC
DEF
Y_START
34
PARAMETER_DEC
DEF
}
# include_file {
VGA_Controller|VGA_Param.h
1123824712
}
# hierarchies {
VGA_Controller:u1
}
# end
# entity
VGA_OSD_RAM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_Controller|VGA_OSD_RAM.v
1123852254
7
# storage
db|DE2_Default.(7).cnf
db|DE2_Default.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
VGA_OSD_RAM:u2
}
# end
# entity
Img_RAM
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_Controller|Img_RAM.v
1124866306
7
# storage
db|DE2_Default.(8).cnf
db|DE2_Default.(8).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
VGA_OSD_RAM:u2|Img_RAM:u0
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|DE2_Default.(9).cnf
db|DE2_Default.(9).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_DEC
USR
WIDTHAD_A
19
PARAMETER_DEC
USR
NUMWORDS_A
307200
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
16
PARAMETER_DEC
USR
NUMWORDS_B
38400
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
Img_DATA.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_B
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_e3f1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
clock1
data_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_e3f1
# case_insensitive
# source_file
db|altsyncram_e3f1.tdf
1152255088
6
# storage
db|DE2_Default.(10).cnf
db|DE2_Default.(10).cnf
# used_port {
wren_a
data_a0
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
address_a12
address_a13
address_a14
address_a15
address_a16
address_a17
address_a18
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
address_b10
address_b11
address_b12
address_b13
address_b14
address_b15
clock0
clock1
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# hierarchies {
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated
}
# end
# entity
altsyncram_8en1
# case_insensitive
# source_file
db|altsyncram_8en1.tdf
1152255088
6
# storage
db|DE2_Default.(11).cnf
db|DE2_Default.(11).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
address_a12
address_a13
address_a14
address_a15
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
address_b10
address_b11
address_b12
address_b13
address_b14
address_b15
address_b16
address_b17
address_b18
clock0
clock1
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_b0
wren_a
wren_b
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
}
# memory_file {
Img_DATA.hex
1126478206
}
# hierarchies {
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1
}
# end
# entity
decode_1qa
# case_insensitive
# source_file
db|decode_1qa.tdf
1152255086
6
# storage
db|DE2_Default.(12).cnf
db|DE2_Default.(12).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
eq8
eq9
eq10
eq11
eq12
eq13
eq14
eq15
eq16
eq17
eq18
eq19
eq20
eq21
eq22
eq23
eq24
eq25
eq26
eq27
eq28
eq29
eq30
eq31
eq32
eq33
eq34
eq35
eq36
eq37
eq38
eq39
eq40
eq41
eq42
eq43
eq44
eq45
eq46
eq47
eq48
eq49
eq50
eq51
eq52
eq53
eq54
eq55
eq56
eq57
eq58
eq59
eq60
eq61
eq62
eq63
eq64
eq65
eq66
eq67
eq68
eq69
eq70
eq71
eq72
eq73
eq74
}
# hierarchies {
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode3
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode4
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a
VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_b
}
# end
# entity
mux_hkb
# case_insensitive
# source_file
db|mux_hkb.tdf
1152255086
6
# storage
db|DE2_Default.(13).cnf
db|DE2_Default.(13).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data30
data31
data32
data33
data34
data35
data36
data37
data38
data39
data40
data41
data42
data43
data44
data45
data46
data47
data48
data49
data50
data51
data52
data53
data54
data55
data56
data57
data58
data59
data60
data61
data62
data63
data64
data65
data66
data67
data68
data69
data70
data71
data72
data73
data74
data75
data76
data77
data78
data79
data80
data81
data82
data83
data84
data85
data86
data87
data88
data89
data90
data91
data92
data93
data94
data95
data96
data97
data98
data99
data100
data101
data102
data103
data104
data105
data106
data107
data108
data109
data110
data111
data112
data113
data114
data115
data116
data117
data118
data119
data120
data121
data122
data123
data124
data125
data126
data127
data128
data129
data130
data131
data132
data133
data134
data135
data136
data137
data138
data139
data140
data141
data142
data143
data144
data145
data146
data147
data148
data149
data150
data151
data152
data153
data154
data155
data156
data157
data158
data159
data160
data161
data162
data163
data164
data165
data166
data167
data168
data169
data170
data171
data172
data173
data174
data175
data176
data177
data178
data179
data180
data181
data182
data183
data184
data185
data186
data187
data188
data189
data190
data191
data192
data193
data194
data195
data196
data197
data198
data199
data200
data201
data202
data203
data204
data205
data206
data207
data208
data209
data210
data211
data212
data213
data214
data215
data216
data217
data218
data219
data220
data221
data222
data223
data224
data225
data226
data227
data228
data229
data230
data231
data232
data233
data234
data235
data236
data237
data238