{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLOCK_50 " "Info: Assuming node \"CLOCK_50\" is an undefined clock" {  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 179 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "AUDIO_DAC:u4\|oAUD_BCK " "Info: Detected ripple clock \"AUDIO_DAC:u4\|oAUD_BCK\" as buffer" {  } { { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 48 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u4\|oAUD_BCK" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "AUDIO_DAC:u4\|LRCK_1X " "Info: Detected ripple clock \"AUDIO_DAC:u4\|LRCK_1X\" as buffer" {  } { { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 72 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u4\|LRCK_1X" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u3\|mI2C_CTRL_CLK " "Info: Detected ripple clock \"I2C_AV_Config:u3\|mI2C_CTRL_CLK\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u3\|mI2C_CTRL_CLK" } } } }  } 0}  } {  } 0}