?? de2_default.tan.qmsg
字號:
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 register VGA_OSD_RAM:u2\|oBlue\[9\] register VGA_Controller:u1\|Cur_Color_B\[9\] 8.843 ns " "Info: Slack time is 8.843 ns for clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" between source register \"VGA_OSD_RAM:u2\|oBlue\[9\]\" and destination register \"VGA_Controller:u1\|Cur_Color_B\[9\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.707 ns + Largest register register " "Info: + Largest register to register requirement is 9.707 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "9.922 ns + " "Info: + Setup relationship between source and destination is 9.922 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 37.358 ns " "Info: + Latch edge is 37.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 39.682 ns -2.324 ns 50 " "Info: Clock period of Destination clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" is 39.682 ns with offset of -2.324 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 27.436 ns " "Info: - Launch edge is 27.436 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 39.682 ns -12.246 ns 50 " "Info: Clock period of Source clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2\" is 39.682 ns with offset of -12.246 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns + Largest " "Info: + Largest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 destination 2.651 ns + Shortest register " "Info: + Shortest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" to destination register is 2.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G9 63 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G9; Fanout = 63; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.548 ns) 2.651 ns VGA_Controller:u1\|Cur_Color_B\[9\] 3 REG LCFF_X17_Y21_N5 1 " "Info: 3: + IC(1.028 ns) + CELL(0.548 ns) = 2.651 ns; Loc. = LCFF_X17_Y21_N5; Fanout = 1; REG Node = 'VGA_Controller:u1\|Cur_Color_B\[9\]'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.576 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } "NODE_NAME" } "" } } { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 60 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.548 ns 20.67 % " "Info: Total cell delay = 0.548 ns ( 20.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.103 ns 79.33 % " "Info: Total interconnect delay = 2.103 ns ( 79.33 % )" { } { } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.651 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.651 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } { 0.000ns 1.075ns 1.028ns } { 0.000ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 source 2.647 ns - Longest register " "Info: - Longest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2\" to source register is 2.647 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 757 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2~clkctrl 2 COMB CLKCTRL_G10 1298 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G10; Fanout = 1298; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2~clkctrl'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 757 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.548 ns) 2.647 ns VGA_OSD_RAM:u2\|oBlue\[9\] 3 REG LCFF_X16_Y21_N31 1 " "Info: 3: + IC(1.024 ns) + CELL(0.548 ns) = 2.647 ns; Loc. = LCFF_X16_Y21_N31; Fanout = 1; REG Node = 'VGA_OSD_RAM:u2\|oBlue\[9\]'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.572 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } "NODE_NAME" } "" } } { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.548 ns 20.70 % " "Info: Total cell delay = 0.548 ns ( 20.70 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.099 ns 79.30 % " "Info: Total interconnect delay = 2.099 ns ( 79.30 % )" { } { } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.647 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.647 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } { 0.000ns 1.075ns 1.024ns } { 0.000ns 0.000ns 0.548ns } } } } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.651 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.651 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } { 0.000ns 1.075ns 1.028ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.647 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.647 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } { 0.000ns 1.075ns 1.024ns } { 0.000ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns - " "Info: - Micro clock to output delay of source is 0.255 ns" { } { { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 24 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 60 -1 0 } } } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.651 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.651 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } { 0.000ns 1.075ns 1.028ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.647 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.647 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } { 0.000ns 1.075ns 1.024ns } { 0.000ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.864 ns - Longest register register " "Info: - Longest register to register delay is 0.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_OSD_RAM:u2\|oBlue\[9\] 1 REG LCFF_X16_Y21_N31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y21_N31; Fanout = 1; REG Node = 'VGA_OSD_RAM:u2\|oBlue\[9\]'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_OSD_RAM:u2|oBlue[9] } "NODE_NAME" } "" } } { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 24 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.491 ns) + CELL(0.373 ns) 0.864 ns VGA_Controller:u1\|Cur_Color_B\[9\] 2 REG LCFF_X17_Y21_N5 1 " "Info: 2: + IC(0.491 ns) + CELL(0.373 ns) = 0.864 ns; Loc. = LCFF_X17_Y21_N5; Fanout = 1; REG Node = 'VGA_Controller:u1\|Cur_Color_B\[9\]'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "0.864 ns" { VGA_OSD_RAM:u2|oBlue[9] VGA_Controller:u1|Cur_Color_B[9] } "NODE_NAME" } "" } } { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 60 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.373 ns 43.17 % " "Info: Total cell delay = 0.373 ns ( 43.17 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.491 ns 56.83 % " "Info: Total interconnect delay = 0.491 ns ( 56.83 % )" { } { } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "0.864 ns" { VGA_OSD_RAM:u2|oBlue[9] VGA_Controller:u1|Cur_Color_B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.864 ns" { VGA_OSD_RAM:u2|oBlue[9] VGA_Controller:u1|Cur_Color_B[9] } { 0.000ns 0.491ns } { 0.000ns 0.373ns } } } } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.651 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.651 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|Cur_Color_B[9] } { 0.000ns 1.075ns 1.028ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.647 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.647 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|oBlue[9] } { 0.000ns 1.075ns 1.024ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "0.864 ns" { VGA_OSD_RAM:u2|oBlue[9] VGA_Controller:u1|Cur_Color_B[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.864 ns" { VGA_OSD_RAM:u2|oBlue[9] VGA_Controller:u1|Cur_Color_B[9] } { 0.000ns 0.491ns } { 0.000ns 0.373ns } } } } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 register AUDIO_DAC:u4\|LRCK_1X_DIV\[1\] register AUDIO_DAC:u4\|LRCK_1X 52.837 ns " "Info: Slack time is 52.837 ns for clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" between source register \"AUDIO_DAC:u4\|LRCK_1X_DIV\[1\]\" and destination register \"AUDIO_DAC:u4\|LRCK_1X\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "367.92 MHz 2.718 ns " "Info: Fmax is 367.92 MHz (period= 2.718 ns)" { } { } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "55.336 ns + Largest register register " "Info: + Largest register to register requirement is 55.336 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "55.555 ns + " "Info: + Setup relationship between source and destination is 55.555 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 53.231 ns " "Info: + Latch edge is 53.231 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 55.555 ns -2.324 ns 50 " "Info: Clock period of Destination clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" is 55.555 ns with offset of -2.324 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0} } { } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.324 ns " "Info: - Launch edge is -2.324 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 55.555 ns -2.324 ns 50 " "Info: Clock period of Source clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" is 55.555 ns with offset of -2.324 ns and duty cycle of 50" { } { } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0} } { } 0} } { } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 destination 2.641 ns + Shortest register " "Info: + Shortest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" to destination register is 2.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 760 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G11 15 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G11; Fanout = 15; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1~clkctrl'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 760 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.548 ns) 2.641 ns AUDIO_DAC:u4\|LRCK_1X 3 REG LCFF_X1_Y23_N29 4 " "Info: 3: + IC(1.018 ns) + CELL(0.548 ns) = 2.641 ns; Loc. = LCFF_X1_Y23_N29; Fanout = 4; REG Node = 'AUDIO_DAC:u4\|LRCK_1X'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.566 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 72 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.548 ns 20.75 % " "Info: Total cell delay = 0.548 ns ( 20.75 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.093 ns 79.25 % " "Info: Total interconnect delay = 2.093 ns ( 79.25 % )" { } { } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } { 0.000ns 1.075ns 1.018ns } { 0.000ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 source 2.641 ns - Longest register " "Info: - Longest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1\" to source register is 2.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 760 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G11 15 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G11; Fanout = 15; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1~clkctrl'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 760 3 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.548 ns) 2.641 ns AUDIO_DAC:u4\|LRCK_1X_DIV\[1\] 3 REG LCFF_X1_Y23_N13 3 " "Info: 3: + IC(1.018 ns) + CELL(0.548 ns) = 2.641 ns; Loc. = LCFF_X1_Y23_N13; Fanout = 3; REG Node = 'AUDIO_DAC:u4\|LRCK_1X_DIV\[1\]'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.566 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } "NODE_NAME" } "" } } { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 55 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.548 ns 20.75 % " "Info: Total cell delay = 0.548 ns ( 20.75 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.093 ns 79.25 % " "Info: Total interconnect delay = 2.093 ns ( 79.25 % )" { } { } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } { 0.000ns 1.075ns 1.018ns } { 0.000ns 0.000ns 0.548ns } } } } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } { 0.000ns 1.075ns 1.018ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } { 0.000ns 1.075ns 1.018ns } { 0.000ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns - " "Info: - Micro clock to output delay of source is 0.255 ns" { } { { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 55 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 72 -1 0 } } } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } { 0.000ns 1.075ns 1.018ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } { 0.000ns 1.075ns 1.018ns } { 0.000ns 0.000ns 0.548ns } } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.499 ns - Longest register register " "Info: - Longest register to register delay is 2.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AUDIO_DAC:u4\|LRCK_1X_DIV\[1\] 1 REG LCFF_X1_Y23_N13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y23_N13; Fanout = 3; REG Node = 'AUDIO_DAC:u4\|LRCK_1X_DIV\[1\]'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { AUDIO_DAC:u4|LRCK_1X_DIV[1] } "NODE_NAME" } "" } } { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 55 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.337 ns) + CELL(0.447 ns) 0.784 ns AUDIO_DAC:u4\|LessThan~297 2 COMB LCCOMB_X1_Y23_N6 1 " "Info: 2: + IC(0.337 ns) + CELL(0.447 ns) = 0.784 ns; Loc. = LCCOMB_X1_Y23_N6; Fanout = 1; COMB Node = 'AUDIO_DAC:u4\|LessThan~297'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "0.784 ns" { AUDIO_DAC:u4|LRCK_1X_DIV[1] AUDIO_DAC:u4|LessThan~297 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.256 ns) + CELL(0.153 ns) 1.193 ns AUDIO_DAC:u4\|LessThan~298 3 COMB LCCOMB_X1_Y23_N0 1 " "Info: 3: + IC(0.256 ns) + CELL(0.153 ns) = 1.193 ns; Loc. = LCCOMB_X1_Y23_N0; Fanout = 1; COMB Node = 'AUDIO_DAC:u4\|LessThan~298'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "0.409 ns" { AUDIO_DAC:u4|LessThan~297 AUDIO_DAC:u4|LessThan~298 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.153 ns) 1.584 ns AUDIO_DAC:u4\|LessThan~299 4 COMB LCCOMB_X1_Y23_N4 10 " "Info: 4: + IC(0.238 ns) + CELL(0.153 ns) = 1.584 ns; Loc. = LCCOMB_X1_Y23_N4; Fanout = 10; COMB Node = 'AUDIO_DAC:u4\|LessThan~299'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "0.391 ns" { AUDIO_DAC:u4|LessThan~298 AUDIO_DAC:u4|LessThan~299 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.242 ns) + CELL(0.673 ns) 2.499 ns AUDIO_DAC:u4\|LRCK_1X 5 REG LCFF_X1_Y23_N29 4 " "Info: 5: + IC(0.242 ns) + CELL(0.673 ns) = 2.499 ns; Loc. = LCFF_X1_Y23_N29; Fanout = 4; REG Node = 'AUDIO_DAC:u4\|LRCK_1X'" { } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "0.915 ns" { AUDIO_DAC:u4|LessThan~299 AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 72 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.426 ns 57.06 % " "Info: Total cell delay = 1.426 ns ( 57.06 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.073 ns 42.94 % " "Info: Total interconnect delay = 1.073 ns ( 42.94 % )" { } { } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.499 ns" { AUDIO_DAC:u4|LRCK_1X_DIV[1] AUDIO_DAC:u4|LessThan~297 AUDIO_DAC:u4|LessThan~298 AUDIO_DAC:u4|LessThan~299 AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.499 ns" { AUDIO_DAC:u4|LRCK_1X_DIV[1] AUDIO_DAC:u4|LessThan~297 AUDIO_DAC:u4|LessThan~298 AUDIO_DAC:u4|LessThan~299 AUDIO_DAC:u4|LRCK_1X } { 0.000ns 0.337ns 0.256ns 0.238ns 0.242ns } { 0.000ns 0.447ns 0.153ns 0.153ns 0.673ns } } } } 0} } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X } { 0.000ns 1.075ns 1.018ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.641 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk1 VGA_Audio_PLL:p1|altpll:altpll_component|_clk1~clkctrl AUDIO_DAC:u4|LRCK_1X_DIV[1] } { 0.000ns 1.075ns 1.018ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.499 ns" { AUDIO_DAC:u4|LRCK_1X_DIV[1] AUDIO_DAC:u4|LessThan~297 AUDIO_DAC:u4|LessThan~298 AUDIO_DAC:u4|LessThan~299 AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.499 ns" { AUDIO_DAC:u4|LRCK_1X_DIV[1] AUDIO_DAC:u4|LessThan~297 AUDIO_DAC:u4|LessThan~298 AUDIO_DAC:u4|LessThan~299 AUDIO_DAC:u4|LRCK_1X } { 0.000ns 0.337ns 0.256ns 0.238ns 0.242ns } { 0.000ns 0.447ns 0.153ns 0.153ns 0.673ns } } } } 0}
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