{ "Info" "ITDB_FULL_SLACK_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 register VGA_Controller:u1\|oAddress\[14\] memory VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|ram_block2a46~porta_address_reg0 24.259 ns " "Info: Slack time is 24.259 ns for clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2\" between source register \"VGA_Controller:u1\|oAddress\[14\]\" and destination memory \"VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|ram_block2a46~porta_address_reg0\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "29.508 ns + Largest register memory " "Info: + Largest register to memory requirement is 29.508 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "29.760 ns + " "Info: + Setup relationship between source and destination is 29.760 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 67.118 ns " "Info: + Latch edge is 67.118 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 39.682 ns -12.246 ns  50 " "Info: Clock period of Destination clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2\" is 39.682 ns with  offset of -12.246 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 37.358 ns " "Info: - Launch edge is 37.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 39.682 ns -2.324 ns  50 " "Info: Clock period of Source clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" is 39.682 ns with  offset of -2.324 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.038 ns + Largest " "Info: + Largest clock skew is 0.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 destination 2.697 ns + Shortest memory " "Info: + Shortest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2\" to destination memory is 2.697 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 757 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2~clkctrl 2 COMB CLKCTRL_G10 1298 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G10; Fanout = 1298; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2~clkctrl'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 757 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.961 ns) + CELL(0.661 ns) 2.697 ns VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|ram_block2a46~porta_address_reg0 3 MEM M4K_X26_Y30 8 " "Info: 3: + IC(0.961 ns) + CELL(0.661 ns) = 2.697 ns; Loc. = M4K_X26_Y30; Fanout = 8; MEM Node = 'VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|ram_block2a46~porta_address_reg0'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.622 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_8en1.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_8en1.tdf" 1718 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.661 ns 24.51 % " "Info: Total cell delay = 0.661 ns ( 24.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.036 ns 75.49 % " "Info: Total interconnect delay = 2.036 ns ( 75.49 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.697 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.697 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } { 0.000ns 1.075ns 0.961ns } { 0.000ns 0.000ns 0.661ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 source 2.659 ns - Longest register " "Info: - Longest clock path from clock \"VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0\" to source register is 2.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 1 CLK PLL_3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.075 ns) + CELL(0.000 ns) 1.075 ns VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G9 63 " "Info: 2: + IC(1.075 ns) + CELL(0.000 ns) = 1.075 ns; Loc. = CLKCTRL_G9; Fanout = 63; COMB Node = 'VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.075 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.548 ns) 2.659 ns VGA_Controller:u1\|oAddress\[14\] 3 REG LCFF_X19_Y19_N11 5 " "Info: 3: + IC(1.036 ns) + CELL(0.548 ns) = 2.659 ns; Loc. = LCFF_X19_Y19_N11; Fanout = 5; REG Node = 'VGA_Controller:u1\|oAddress\[14\]'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.584 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } "NODE_NAME" } "" } } { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.548 ns 20.61 % " "Info: Total cell delay = 0.548 ns ( 20.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.111 ns 79.39 % " "Info: Total interconnect delay = 2.111 ns ( 79.39 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.659 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.659 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } { 0.000ns 1.075ns 1.036ns } { 0.000ns 0.000ns 0.548ns } } }  } 0}  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.697 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.697 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } { 0.000ns 1.075ns 0.961ns } { 0.000ns 0.000ns 0.661ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.659 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.659 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } { 0.000ns 1.075ns 1.036ns } { 0.000ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.255 ns - " "Info: - Micro clock to output delay of source is 0.255 ns" {  } { { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 30 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.035 ns - " "Info: - Micro setup delay of destination is 0.035 ns" {  } { { "db/altsyncram_8en1.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_8en1.tdf" 1718 2 0 } }  } 0}  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.697 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.697 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } { 0.000ns 1.075ns 0.961ns } { 0.000ns 0.000ns 0.661ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.659 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.659 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } { 0.000ns 1.075ns 1.036ns } { 0.000ns 0.000ns 0.548ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.249 ns - Longest register memory " "Info: - Longest register to memory delay is 5.249 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGA_Controller:u1\|oAddress\[14\] 1 REG LCFF_X19_Y19_N11 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y19_N11; Fanout = 5; REG Node = 'VGA_Controller:u1\|oAddress\[14\]'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Controller:u1|oAddress[14] } "NODE_NAME" } "" } } { "VGA_Controller/VGA_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_Controller.v" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.796 ns) + CELL(0.447 ns) 1.243 ns VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|decode_1qa:decode_a\|w_anode3960w\[3\]~36 2 COMB LCCOMB_X21_Y19_N4 18 " "Info: 2: + IC(0.796 ns) + CELL(0.447 ns) = 1.243 ns; Loc. = LCCOMB_X21_Y19_N4; Fanout = 18; COMB Node = 'VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|decode_1qa:decode_a\|w_anode3960w\[3\]~36'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.243 ns" { VGA_Controller:u1|oAddress[14] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode3960w[3]~36 } "NODE_NAME" } "" } } { "db/decode_1qa.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/decode_1qa.tdf" 42 14 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.428 ns) 2.395 ns VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|decode_1qa:decode_a\|w_anode4416w\[3\] 3 COMB LCCOMB_X18_Y19_N28 9 " "Info: 3: + IC(0.724 ns) + CELL(0.428 ns) = 2.395 ns; Loc. = LCCOMB_X18_Y19_N28; Fanout = 9; COMB Node = 'VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|decode_1qa:decode_a\|w_anode4416w\[3\]'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "1.152 ns" { VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode3960w[3]~36 VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode4416w[3] } "NODE_NAME" } "" } } { "db/decode_1qa.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/decode_1qa.tdf" 86 14 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.222 ns) + CELL(0.632 ns) 5.249 ns VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|ram_block2a46~porta_address_reg0 4 MEM M4K_X26_Y30 8 " "Info: 4: + IC(2.222 ns) + CELL(0.632 ns) = 5.249 ns; Loc. = M4K_X26_Y30; Fanout = 8; MEM Node = 'VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|ram_block2a46~porta_address_reg0'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.854 ns" { VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode4416w[3] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_8en1.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_8en1.tdf" 1718 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.507 ns 28.71 % " "Info: Total cell delay = 1.507 ns ( 28.71 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.742 ns 71.29 % " "Info: Total interconnect delay = 3.742 ns ( 71.29 % )" {  } {  } 0}  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "5.249 ns" { VGA_Controller:u1|oAddress[14] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode3960w[3]~36 VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode4416w[3] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.249 ns" { VGA_Controller:u1|oAddress[14] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode3960w[3]~36 VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode4416w[3] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } { 0.000ns 0.796ns 0.724ns 2.222ns } { 0.000ns 0.447ns 0.428ns 0.632ns } } }  } 0}  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.697 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.697 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk2 VGA_Audio_PLL:p1|altpll:altpll_component|_clk2~clkctrl VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } { 0.000ns 1.075ns 0.961ns } { 0.000ns 0.000ns 0.661ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "2.659 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.659 ns" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 VGA_Audio_PLL:p1|altpll:altpll_component|_clk0~clkctrl VGA_Controller:u1|oAddress[14] } { 0.000ns 1.075ns 1.036ns } { 0.000ns 0.000ns 0.548ns } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "5.249 ns" { VGA_Controller:u1|oAddress[14] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode3960w[3]~36 VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode4416w[3] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.249 ns" { VGA_Controller:u1|oAddress[14] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode3960w[3]~36 VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|decode_1qa:decode_a|w_anode4416w[3] VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1|ram_block2a46~porta_address_reg0 } { 0.000ns 0.796ns 0.724ns 2.222ns } { 0.000ns 0.447ns 0.428ns 0.632ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLOCK_27 " "Info: No valid register-to-register data paths exist for clock \"CLOCK_27\"" {  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 memory I2C_AV_Config:u3\|I2C_Controller:u0\|SD\[3\] register I2C_AV_Config:u3\|I2C_Controller:u0\|SDO~reg0 208.72 MHz 4.791 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 208.72 MHz between source memory \"I2C_AV_Config:u3\|I2C_Controller:u0\|SD\[3\]\" and destination register \"I2C_AV_Config:u3\|I2C_Controller:u0\|SDO~reg0\" (period= 4.791 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.603 ns + Longest memory register " "Info: + Longest memory to register delay is 4.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.088 ns) 0.088 ns I2C_AV_Config:u3\|I2C_Controller:u0\|SD\[3\] 1 MEM M4K_X13_Y29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.088 ns) = 0.088 ns; Loc. = M4K_X13_Y29; Fanout = 1; MEM Node = 'I2C_AV_Config:u3\|I2C_Controller:u0\|SD\[3\]'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { I2C_AV_Config:u3|I2C_Controller:u0|SD[3] } "NODE_NAME" } "" } } { "I2C_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_Controller.v" 74 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.428 ns) 1.447 ns I2C_AV_Config:u3\|I2C_Controller:u0\|Select~2904 2 COMB LCCOMB_X15_Y28_N22 1 " "Info: 2: + IC(0.931 ns) + CELL(0.428 ns) = 1.447 ns; Loc. = LCCOMB_X15_Y28_N22; Fanout = 1; COMB Node = 'I2C_AV_Config:u3\|I2C_Controller:u0\|Select~2904'" {  } { { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Defau