{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 07 14:52:36 2006 " "Info: Processing started: Fri Jul 07 14:52:36 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE2_Default -c DE2_Default " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_Default -c DE2_Default" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_Default EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"DE2_Default\"" {  } {  } 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 14 15 0 0 " "Info: Implementing clock multiplication of 14, clock division of 15, and phase shift of 0 degrees (0 ps) for VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 2 3 0 0 " "Info: Implementing clock multiplication of 2, clock division of 3, and phase shift of 0 degrees (0 ps) for VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 760 3 0 } }  } 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 14 15 -90 -9921 " "Info: Implementing clock multiplication of 14, clock division of 15, and phase shift of -90 degrees (-9921 ps) for VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 port" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 757 3 0 } }  } 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_3) " "Info: Automatically promoted node VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0 (placed in counter C0 of PLL_3)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" {  } {  } 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 (placed in counter C1 of PLL_3) " "Info: Automatically promoted node VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk1 (placed in counter C1 of PLL_3)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G11 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G11" {  } {  } 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 (placed in counter C2 of PLL_3) " "Info: Automatically promoted node VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk2 (placed in counter C2 of PLL_3)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G10 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G10" {  } {  } 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "VGA_Audio_PLL:p1\|altpll:altpll_component\|_clk0" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { VGA_Audio_PLL:p1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0}  } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 179 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { CLOCK_50 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { CLOCK_50 } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "I2C_AV_Config:u3\|mI2C_CTRL_CLK  " "Info: Automatically promoted node I2C_AV_Config:u3\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u3\|I2C_Controller:u0\|I2C_SCLK~257 " "Info: Destination node I2C_AV_Config:u3\|I2C_Controller:u0\|I2C_SCLK~257" {  } { { "I2C_Controller.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_Controller.v" 62 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u3\|I2C_Controller:u0\|I2C_SCLK~257" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { I2C_AV_Config:u3|I2C_Controller:u0|I2C_SCLK~257 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { I2C_AV_Config:u3|I2C_Controller:u0|I2C_SCLK~257 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u3\|mI2C_CTRL_CLK~5 " "Info: Destination node I2C_AV_Config:u3\|mI2C_CTRL_CLK~5" {  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u3\|mI2C_CTRL_CLK~5" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { I2C_AV_Config:u3|mI2C_CTRL_CLK~5 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { I2C_AV_Config:u3|mI2C_CTRL_CLK~5 } "NODE_NAME" } }  } 0}  } {  } 0}  } { { "I2C_AV_Config.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/I2C_AV_Config.v" 16 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u3\|mI2C_CTRL_CLK" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { I2C_AV_Config:u3|mI2C_CTRL_CLK } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { I2C_AV_Config:u3|mI2C_CTRL_CLK } "NODE_NAME" } }  } 0}