?? de2_default.fit.qmsg
字號:
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "AUDIO_DAC:u4\|LRCK_1X " "Info: Automatically promoted node AUDIO_DAC:u4\|LRCK_1X " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "AUD_DACLRCK " "Info: Destination node AUD_DACLRCK" { } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 290 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { AUD_DACLRCK } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "AUD_ADCLRCK " "Info: Destination node AUD_ADCLRCK" { } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 288 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { AUD_ADCLRCK } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "AUDIO_DAC:u4\|LRCK_1X~3 " "Info: Destination node AUDIO_DAC:u4\|LRCK_1X~3" { } { { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 72 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u4\|LRCK_1X~3" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { AUDIO_DAC:u4|LRCK_1X~3 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { AUDIO_DAC:u4|LRCK_1X~3 } "NODE_NAME" } } } 0} } { } 0} } { { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 72 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u4\|LRCK_1X" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { AUDIO_DAC:u4|LRCK_1X } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "AUDIO_DAC:u4\|oAUD_BCK " "Info: Automatically promoted node AUDIO_DAC:u4\|oAUD_BCK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: The following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "AUD_BCLK " "Info: Destination node AUD_BCLK" { } { { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 292 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { AUD_BCLK } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { AUD_BCLK } "NODE_NAME" } } } 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "AUDIO_DAC:u4\|oAUD_BCK~3 " "Info: Destination node AUDIO_DAC:u4\|oAUD_BCK~3" { } { { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 48 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u4\|oAUD_BCK~3" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { AUDIO_DAC:u4|oAUD_BCK~3 } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { AUDIO_DAC:u4|oAUD_BCK~3 } "NODE_NAME" } } } 0} } { } 0} } { { "AUDIO_DAC.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/AUDIO_DAC.v" 48 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "AUDIO_DAC:u4\|oAUD_BCK" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { AUDIO_DAC:u4|oAUD_BCK } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { AUDIO_DAC:u4|oAUD_BCK } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Reset_Delay:r0\|oRESET " "Info: Automatically promoted node Reset_Delay:r0\|oRESET " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0} } { { "Reset_Delay.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/Reset_Delay.v" 3 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Reset_Delay:r0\|oRESET" } } } } { "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" "" { Report "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default_cmp.qrpt" Compiler "DE2_Default" "UNKNOWN" "V1" "E:/zhangwei/fpga_pro/DE2_Default/db/DE2_Default.quartus_db" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/" "" "" { Reset_Delay:r0|oRESET } "NODE_NAME" } "" } } { "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" { Floorplan "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.fld" "" "" { Reset_Delay:r0|oRESET } "NODE_NAME" } } } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" { } { } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" { } { } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" { } { } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" { } { } 0}
{ "Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 0}
{ "Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll clk\[1\] AUD_XCK " "Warning: PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" output port clk\[1\] feeds output pin \"AUD_XCK\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance." { } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "VGA_Audio_PLL.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Audio_PLL.v" 89 -1 0 } } { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 346 -1 0 } } { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 293 -1 0 } } } 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "VGA_Audio_PLL:p1\|altpll:altpll_component\|pll clk\[2\] VGA_CLK " "Warning: PLL \"VGA_Audio_PLL:p1\|altpll:altpll_component\|pll\" output port clk\[2\] feeds output pin \"VGA_CLK\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance." { } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "VGA_Audio_PLL.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Audio_PLL.v" 89 -1 0 } } { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 346 -1 0 } } { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 270 -1 0 } } } 0}
{ "Warning" "WCUT_CUT_RAM_PORT_STUCK_AT_VCC_OR_GND" "VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|ram_block2a74 clk1 GND " "Warning: WYSIWYG primitive \"VGA_OSD_RAM:u2\|Img_RAM:u0\|altsyncram:altsyncram_component\|altsyncram_e3f1:auto_generated\|altsyncram_8en1:altsyncram1\|ram_block2a74\" has port clk1 that is stuck at GND" { } { { "db/altsyncram_8en1.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_8en1.tdf" 2726 2 0 } } { "db/altsyncram_e3f1.tdf" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/db/altsyncram_e3f1.tdf" 35 2 0 } } { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "VGA_Controller/Img_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/Img_RAM.v" 79 -1 0 } } { "VGA_Controller/VGA_OSD_RAM.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/VGA_Controller/VGA_OSD_RAM.v" 74 -1 0 } } { "DE2_Default.v" "" { Text "E:/zhangwei/fpga_pro/DE2_Default/DE2_Default.v" 382 -1 0 } } } 0}
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