|DE2_Default
CLOCK_27 => CLOCK_27~0.IN1
CLOCK_50 => CLOCK_50~0.IN3
EXT_CLOCK => ~NO_FANOUT~
KEY[0] => KEY[0]~0.IN1
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
SW[0] => ~NO_FANOUT~
SW[1] => ~NO_FANOUT~
SW[2] => ~NO_FANOUT~
SW[3] => ~NO_FANOUT~
SW[4] => ~NO_FANOUT~
SW[5] => ~NO_FANOUT~
SW[6] => ~NO_FANOUT~
SW[7] => ~NO_FANOUT~
SW[8] => ~NO_FANOUT~
SW[9] => ~NO_FANOUT~
SW[10] => ~NO_FANOUT~
SW[11] => ~NO_FANOUT~
SW[12] => ~NO_FANOUT~
SW[13] => ~NO_FANOUT~
SW[14] => ~NO_FANOUT~
SW[15] => ~NO_FANOUT~
SW[16] => ~NO_FANOUT~
SW[17] => SW[17]~0.IN1
HEX0[0] <= SEG7_LUT_8:u0.port0
HEX0[1] <= SEG7_LUT_8:u0.port0
HEX0[2] <= SEG7_LUT_8:u0.port0
HEX0[3] <= SEG7_LUT_8:u0.port0
HEX0[4] <= SEG7_LUT_8:u0.port0
HEX0[5] <= SEG7_LUT_8:u0.port0
HEX0[6] <= SEG7_LUT_8:u0.port0
HEX1[0] <= SEG7_LUT_8:u0.port1
HEX1[1] <= SEG7_LUT_8:u0.port1
HEX1[2] <= SEG7_LUT_8:u0.port1
HEX1[3] <= SEG7_LUT_8:u0.port1
HEX1[4] <= SEG7_LUT_8:u0.port1
HEX1[5] <= SEG7_LUT_8:u0.port1
HEX1[6] <= SEG7_LUT_8:u0.port1
HEX2[0] <= SEG7_LUT_8:u0.port2
HEX2[1] <= SEG7_LUT_8:u0.port2
HEX2[2] <= SEG7_LUT_8:u0.port2
HEX2[3] <= SEG7_LUT_8:u0.port2
HEX2[4] <= SEG7_LUT_8:u0.port2
HEX2[5] <= SEG7_LUT_8:u0.port2
HEX2[6] <= SEG7_LUT_8:u0.port2
HEX3[0] <= SEG7_LUT_8:u0.port3
HEX3[1] <= SEG7_LUT_8:u0.port3
HEX3[2] <= SEG7_LUT_8:u0.port3
HEX3[3] <= SEG7_LUT_8:u0.port3
HEX3[4] <= SEG7_LUT_8:u0.port3
HEX3[5] <= SEG7_LUT_8:u0.port3
HEX3[6] <= SEG7_LUT_8:u0.port3
HEX4[0] <= SEG7_LUT_8:u0.port4
HEX4[1] <= SEG7_LUT_8:u0.port4
HEX4[2] <= SEG7_LUT_8:u0.port4
HEX4[3] <= SEG7_LUT_8:u0.port4
HEX4[4] <= SEG7_LUT_8:u0.port4
HEX4[5] <= SEG7_LUT_8:u0.port4
HEX4[6] <= SEG7_LUT_8:u0.port4
HEX5[0] <= SEG7_LUT_8:u0.port5
HEX5[1] <= SEG7_LUT_8:u0.port5
HEX5[2] <= SEG7_LUT_8:u0.port5
HEX5[3] <= SEG7_LUT_8:u0.port5
HEX5[4] <= SEG7_LUT_8:u0.port5
HEX5[5] <= SEG7_LUT_8:u0.port5
HEX5[6] <= SEG7_LUT_8:u0.port5
HEX6[0] <= SEG7_LUT_8:u0.port6
HEX6[1] <= SEG7_LUT_8:u0.port6
HEX6[2] <= SEG7_LUT_8:u0.port6
HEX6[3] <= SEG7_LUT_8:u0.port6
HEX6[4] <= SEG7_LUT_8:u0.port6
HEX6[5] <= SEG7_LUT_8:u0.port6
HEX6[6] <= SEG7_LUT_8:u0.port6
HEX7[0] <= SEG7_LUT_8:u0.port7
HEX7[1] <= SEG7_LUT_8:u0.port7
HEX7[2] <= SEG7_LUT_8:u0.port7
HEX7[3] <= SEG7_LUT_8:u0.port7
HEX7[4] <= SEG7_LUT_8:u0.port7
HEX7[5] <= SEG7_LUT_8:u0.port7
HEX7[6] <= SEG7_LUT_8:u0.port7
LEDG[0] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDG[2] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
LEDG[3] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDG[4] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDG[5] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
LEDG[6] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDG[7] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDG[8] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[0] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDR[1] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[2] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[3] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDR[4] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[5] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[6] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDR[7] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[8] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[9] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDR[10] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[11] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[12] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDR[13] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[14] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[15] <= Cont[23].DB_MAX_OUTPUT_PORT_TYPE
LEDR[16] <= mSEG7_DIG[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[17] <= mSEG7_DIG[1].DB_MAX_OUTPUT_PORT_TYPE
UART_TXD <= <GND>
UART_RXD => ~NO_FANOUT~
IRDA_TXD <= <GND>
IRDA_RXD => ~NO_FANOUT~
DRAM_DQ[0] <= DRAM_DQ~32
DRAM_DQ[1] <= DRAM_DQ~31
DRAM_DQ[2] <= DRAM_DQ~30
DRAM_DQ[3] <= DRAM_DQ~29
DRAM_DQ[4] <= DRAM_DQ~28
DRAM_DQ[5] <= DRAM_DQ~27
DRAM_DQ[6] <= DRAM_DQ~26
DRAM_DQ[7] <= DRAM_DQ~25
DRAM_DQ[8] <= DRAM_DQ~24
DRAM_DQ[9] <= DRAM_DQ~23
DRAM_DQ[10] <= DRAM_DQ~22
DRAM_DQ[11] <= DRAM_DQ~21
DRAM_DQ[12] <= DRAM_DQ~20
DRAM_DQ[13] <= DRAM_DQ~19
DRAM_DQ[14] <= DRAM_DQ~18
DRAM_DQ[15] <= DRAM_DQ~17
DRAM_ADDR[0] <= <GND>
DRAM_ADDR[1] <= <GND>
DRAM_ADDR[2] <= <GND>
DRAM_ADDR[3] <= <GND>
DRAM_ADDR[4] <= <GND>
DRAM_ADDR[5] <= <GND>
DRAM_ADDR[6] <= <GND>
DRAM_ADDR[7] <= <GND>
DRAM_ADDR[8] <= <GND>
DRAM_ADDR[9] <= <GND>
DRAM_ADDR[10] <= <GND>
DRAM_ADDR[11] <= <GND>
DRAM_LDQM <= <GND>
DRAM_UDQM <= <GND>
DRAM_WE_N <= <GND>
DRAM_CAS_N <= <GND>
DRAM_RAS_N <= <GND>
DRAM_CS_N <= <GND>
DRAM_BA_0 <= <GND>
DRAM_BA_1 <= <GND>
DRAM_CLK <= <GND>
DRAM_CKE <= <GND>
FL_DQ[0] <= FL_DQ~15
FL_DQ[1] <= FL_DQ~14
FL_DQ[2] <= FL_DQ~13
FL_DQ[3] <= FL_DQ~12
FL_DQ[4] <= FL_DQ~11
FL_DQ[5] <= FL_DQ~10
FL_DQ[6] <= FL_DQ~9
FL_DQ[7] <= FL_DQ~8
FL_ADDR[0] <= <GND>
FL_ADDR[1] <= <GND>
FL_ADDR[2] <= <GND>
FL_ADDR[3] <= <GND>
FL_ADDR[4] <= <GND>
FL_ADDR[5] <= <GND>
FL_ADDR[6] <= <GND>
FL_ADDR[7] <= <GND>
FL_ADDR[8] <= <GND>
FL_ADDR[9] <= <GND>
FL_ADDR[10] <= <GND>
FL_ADDR[11] <= <GND>
FL_ADDR[12] <= <GND>
FL_ADDR[13] <= <GND>
FL_ADDR[14] <= <GND>
FL_ADDR[15] <= <GND>
FL_ADDR[16] <= <GND>
FL_ADDR[17] <= <GND>
FL_ADDR[18] <= <GND>
FL_ADDR[19] <= <GND>
FL_ADDR[20] <= <GND>
FL_ADDR[21] <= <GND>
FL_WE_N <= <GND>
FL_RST_N <= <GND>
FL_OE_N <= <GND>
FL_CE_N <= <GND>
SRAM_DQ[0] <= SRAM_DQ~31
SRAM_DQ[1] <= SRAM_DQ~30
SRAM_DQ[2] <= SRAM_DQ~29
SRAM_DQ[3] <= SRAM_DQ~28
SRAM_DQ[4] <= SRAM_DQ~27
SRAM_DQ[5] <= SRAM_DQ~26
SRAM_DQ[6] <= SRAM_DQ~25
SRAM_DQ[7] <= SRAM_DQ~24
SRAM_DQ[8] <= SRAM_DQ~23
SRAM_DQ[9] <= SRAM_DQ~22
SRAM_DQ[10] <= SRAM_DQ~21
SRAM_DQ[11] <= SRAM_DQ~20
SRAM_DQ[12] <= SRAM_DQ~19
SRAM_DQ[13] <= SRAM_DQ~18
SRAM_DQ[14] <= SRAM_DQ~17
SRAM_DQ[15] <= SRAM_DQ~16
SRAM_ADDR[0] <= <GND>
SRAM_ADDR[1] <= <GND>
SRAM_ADDR[2] <= <GND>
SRAM_ADDR[3] <= <GND>
SRAM_ADDR[4] <= <GND>
SRAM_ADDR[5] <= <GND>
SRAM_ADDR[6] <= <GND>
SRAM_ADDR[7] <= <GND>
SRAM_ADDR[8] <= <GND>
SRAM_ADDR[9] <= <GND>
SRAM_ADDR[10] <= <GND>
SRAM_ADDR[11] <= <GND>
SRAM_ADDR[12] <= <GND>
SRAM_ADDR[13] <= <GND>
SRAM_ADDR[14] <= <GND>
SRAM_ADDR[15] <= <GND>
SRAM_ADDR[16] <= <GND>
SRAM_ADDR[17] <= <GND>
SRAM_UB_N <= <GND>
SRAM_LB_N <= <GND>
SRAM_WE_N <= <GND>
SRAM_CE_N <= <GND>
SRAM_OE_N <= <GND>
OTG_DATA[0] <= OTG_DATA~31
OTG_DATA[1] <= OTG_DATA~30
OTG_DATA[2] <= OTG_DATA~29
OTG_DATA[3] <= OTG_DATA~28
OTG_DATA[4] <= OTG_DATA~27
OTG_DATA[5] <= OTG_DATA~26
OTG_DATA[6] <= OTG_DATA~25
OTG_DATA[7] <= OTG_DATA~24
OTG_DATA[8] <= OTG_DATA~23
OTG_DATA[9] <= OTG_DATA~22
OTG_DATA[10] <= OTG_DATA~21
OTG_DATA[11] <= OTG_DATA~20
OTG_DATA[12] <= OTG_DATA~19
OTG_DATA[13] <= OTG_DATA~18
OTG_DATA[14] <= OTG_DATA~17
OTG_DATA[15] <= OTG_DATA~16
OTG_ADDR[0] <= <GND>
OTG_ADDR[1] <= <GND>
OTG_CS_N <= <GND>
OTG_RD_N <= <GND>
OTG_WR_N <= <GND>
OTG_RST_N <= <GND>
OTG_FSPEED <= <GND>
OTG_LSPEED <= <GND>
OTG_INT0 => ~NO_FANOUT~
OTG_INT1 => ~NO_FANOUT~
OTG_DREQ0 => ~NO_FANOUT~
OTG_DREQ1 => ~NO_FANOUT~
OTG_DACK0_N <= <GND>
OTG_DACK1_N <= <GND>
LCD_ON <= <VCC>
LCD_BLON <= <VCC>
LCD_RW <= LCD_TEST:u5.LCD_RW
LCD_EN <= LCD_TEST:u5.LCD_EN
LCD_RS <= LCD_TEST:u5.LCD_RS
LCD_DATA[0] <= LCD_TEST:u5.LCD_DATA
LCD_DATA[1] <= LCD_TEST:u5.LCD_DATA
LCD_DATA[2] <= LCD_TEST:u5.LCD_DATA
LCD_DATA[3] <= LCD_TEST:u5.LCD_DATA
LCD_DATA[4] <= LCD_TEST:u5.LCD_DATA
LCD_DATA[5] <= LCD_TEST:u5.LCD_DATA
LCD_DATA[6] <= LCD_TEST:u5.LCD_DATA
LCD_DATA[7] <= LCD_TEST:u5.LCD_DATA
SD_DAT <= SD_DAT~0
SD_DAT3 <= <UNC>
SD_CMD <= <UNC>
SD_CLK <= <GND>
TDI => ~NO_FANOUT~
TCK => ~NO_FANOUT~
TCS => ~NO_FANOUT~
TDO <= <GND>
I2C_SDAT <= I2C_AV_Config:u3.I2C_SDAT
I2C_SCLK <= I2C_AV_Config:u3.I2C_SCLK
PS2_DAT => ~NO_FANOUT~
PS2_CLK => ~NO_FANOUT~
VGA_CLK <= VGA_CLK~0.DB_MAX_OUTPUT_PORT_TYPE
VGA_HS <= VGA_Controller:u1.oVGA_H_SYNC
VGA_VS <= VGA_Controller:u1.oVGA_V_SYNC
VGA_BLANK <= VGA_Controller:u1.oVGA_BLANK
VGA_SYNC <= VGA_Controller:u1.oVGA_SYNC
VGA_R[0] <= VGA_Controller:u1.oVGA_R
VGA_R[1] <= VGA_Controller:u1.oVGA_R
VGA_R[2] <= VGA_Controller:u1.oVGA_R
VGA_R[3] <= VGA_Controller:u1.oVGA_R
VGA_R[4] <= VGA_Controller:u1.oVGA_R
VGA_R[5] <= VGA_Controller:u1.oVGA_R
VGA_R[6] <= VGA_Controller:u1.oVGA_R
VGA_R[7] <= VGA_Controller:u1.oVGA_R
VGA_R[8] <= VGA_Controller:u1.oVGA_R
VGA_R[9] <= VGA_Controller:u1.oVGA_R
VGA_G[0] <= VGA_Controller:u1.oVGA_G
VGA_G[1] <= VGA_Controller:u1.oVGA_G
VGA_G[2] <= VGA_Controller:u1.oVGA_G
VGA_G[3] <= VGA_Controller:u1.oVGA_G
VGA_G[4] <= VGA_Controller:u1.oVGA_G
VGA_G[5] <= VGA_Controller:u1.oVGA_G
VGA_G[6] <= VGA_Controller:u1.oVGA_G
VGA_G[7] <= VGA_Controller:u1.oVGA_G
VGA_G[8] <= VGA_Controller:u1.oVGA_G
VGA_G[9] <= VGA_Controller:u1.oVGA_G
VGA_B[0] <= VGA_Controller:u1.oVGA_B
VGA_B[1] <= VGA_Controller:u1.oVGA_B
VGA_B[2] <= VGA_Controller:u1.oVGA_B
VGA_B[3] <= VGA_Controller:u1.oVGA_B
VGA_B[4] <= VGA_Controller:u1.oVGA_B
VGA_B[5] <= VGA_Controller:u1.oVGA_B
VGA_B[6] <= VGA_Controller:u1.oVGA_B
VGA_B[7] <= VGA_Controller:u1.oVGA_B
VGA_B[8] <= VGA_Controller:u1.oVGA_B
VGA_B[9] <= VGA_Controller:u1.oVGA_B
ENET_DATA[0] <= ENET_DATA~31
ENET_DATA[1] <= ENET_DATA~30
ENET_DATA[2] <= ENET_DATA~29
ENET_DATA[3] <= ENET_DATA~28
ENET_DATA[4] <= ENET_DATA~27
ENET_DATA[5] <= ENET_DATA~26
ENET_DATA[6] <= ENET_DATA~25
ENET_DATA[7] <= ENET_DATA~24
ENET_DATA[8] <= ENET_DATA~23
ENET_DATA[9] <= ENET_DATA~22
ENET_DATA[10] <= ENET_DATA~21
ENET_DATA[11] <= ENET_DATA~20
ENET_DATA[12] <= ENET_DATA~19
ENET_DATA[13] <= ENET_DATA~18
ENET_DATA[14] <= ENET_DATA~17
ENET_DATA[15] <= ENET_DATA~16
ENET_CMD <= <GND>
ENET_CS_N <= <GND>
ENET_WR_N <= <GND>
ENET_RD_N <= <GND>
ENET_RST_N <= <GND>
ENET_INT => ~NO_FANOUT~
ENET_CLK <= <GND>
AUD_ADCLRCK <= AUD_DACLRCK~0.DB_MAX_OUTPUT_PORT_TYPE
AUD_ADCDAT => ~NO_FANOUT~
AUD_DACLRCK <= AUDIO_DAC:u4.oAUD_LRCK
AUD_DACDAT <= AUDIO_DAC:u4.oAUD_DATA
AUD_BCLK <= AUDIO_DAC:u4.oAUD_BCK
AUD_XCK <= AUD_CTRL_CLK.DB_MAX_OUTPUT_PORT_TYPE
TD_DATA[0] => ~NO_FANOUT~
TD_DATA[1] => ~NO_FANOUT~
TD_DATA[2] => ~NO_FANOUT~
TD_DATA[3] => ~NO_FANOUT~
TD_DATA[4] => ~NO_FANOUT~
TD_DATA[5] => ~NO_FANOUT~
TD_DATA[6] => ~NO_FANOUT~
TD_DATA[7] => ~NO_FANOUT~
TD_HS => ~NO_FANOUT~
TD_VS => ~NO_FANOUT~
TD_RESET <= <VCC>
GPIO_0[0] <= GPIO_0~71
GPIO_0[1] <= GPIO_0~70
GPIO_0[2] <= GPIO_0~69
GPIO_0[3] <= GPIO_0~68
GPIO_0[4] <= GPIO_0~67
GPIO_0[5] <= GPIO_0~66
GPIO_0[6] <= GPIO_0~65
GPIO_0[7] <= GPIO_0~64
GPIO_0[8] <= GPIO_0~63
GPIO_0[9] <= GPIO_0~62
GPIO_0[10] <= GPIO_0~61
GPIO_0[11] <= GPIO_0~60
GPIO_0[12] <= GPIO_0~59
GPIO_0[13] <= GPIO_0~58
GPIO_0[14] <= GPIO_0~57
GPIO_0[15] <= GPIO_0~56
GPIO_0[16] <= GPIO_0~55
GPIO_0[17] <= GPIO_0~54
GPIO_0[18] <= GPIO_0~53