GPIO_0[19] <= GPIO_0~52
GPIO_0[20] <= GPIO_0~51
GPIO_0[21] <= GPIO_0~50
GPIO_0[22] <= GPIO_0~49
GPIO_0[23] <= GPIO_0~48
GPIO_0[24] <= GPIO_0~47
GPIO_0[25] <= GPIO_0~46
GPIO_0[26] <= GPIO_0~45
GPIO_0[27] <= GPIO_0~44
GPIO_0[28] <= GPIO_0~43
GPIO_0[29] <= GPIO_0~42
GPIO_0[30] <= GPIO_0~41
GPIO_0[31] <= GPIO_0~40
GPIO_0[32] <= GPIO_0~39
GPIO_0[33] <= GPIO_0~38
GPIO_0[34] <= GPIO_0~37
GPIO_0[35] <= GPIO_0~36
GPIO_1[0] <= GPIO_1~71
GPIO_1[1] <= GPIO_1~70
GPIO_1[2] <= GPIO_1~69
GPIO_1[3] <= GPIO_1~68
GPIO_1[4] <= GPIO_1~67
GPIO_1[5] <= GPIO_1~66
GPIO_1[6] <= GPIO_1~65
GPIO_1[7] <= GPIO_1~64
GPIO_1[8] <= GPIO_1~63
GPIO_1[9] <= GPIO_1~62
GPIO_1[10] <= GPIO_1~61
GPIO_1[11] <= GPIO_1~60
GPIO_1[12] <= GPIO_1~59
GPIO_1[13] <= GPIO_1~58
GPIO_1[14] <= GPIO_1~57
GPIO_1[15] <= GPIO_1~56
GPIO_1[16] <= GPIO_1~55
GPIO_1[17] <= GPIO_1~54
GPIO_1[18] <= GPIO_1~53
GPIO_1[19] <= GPIO_1~52
GPIO_1[20] <= GPIO_1~51
GPIO_1[21] <= GPIO_1~50
GPIO_1[22] <= GPIO_1~49
GPIO_1[23] <= GPIO_1~48
GPIO_1[24] <= GPIO_1~47
GPIO_1[25] <= GPIO_1~46
GPIO_1[26] <= GPIO_1~45
GPIO_1[27] <= GPIO_1~44
GPIO_1[28] <= GPIO_1~43
GPIO_1[29] <= GPIO_1~42
GPIO_1[30] <= GPIO_1~41
GPIO_1[31] <= GPIO_1~40
GPIO_1[32] <= GPIO_1~39
GPIO_1[33] <= GPIO_1~38
GPIO_1[34] <= GPIO_1~37
GPIO_1[35] <= GPIO_1~36


|DE2_Default|Reset_Delay:r0
iCLK => Cont[18].CLK
iCLK => Cont[17].CLK
iCLK => Cont[16].CLK
iCLK => Cont[15].CLK
iCLK => Cont[14].CLK
iCLK => Cont[13].CLK
iCLK => Cont[12].CLK
iCLK => Cont[11].CLK
iCLK => Cont[10].CLK
iCLK => Cont[9].CLK
iCLK => Cont[8].CLK
iCLK => Cont[7].CLK
iCLK => Cont[6].CLK
iCLK => Cont[5].CLK
iCLK => Cont[4].CLK
iCLK => Cont[3].CLK
iCLK => Cont[2].CLK
iCLK => Cont[1].CLK
iCLK => Cont[0].CLK
iCLK => oRESET~reg0.CLK
iCLK => Cont[19].CLK
oRESET <= oRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DE2_Default|VGA_Audio_PLL:p1
areset => areset~0.IN1
inclk0 => sub_wire5[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
c2 <= altpll:altpll_component.clk


|DE2_Default|VGA_Audio_PLL:p1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => pll.ARESET
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>


|DE2_Default|SEG7_LUT_8:u0
oSEG0[0] <= SEG7_LUT:u0.port0
oSEG0[1] <= SEG7_LUT:u0.port0
oSEG0[2] <= SEG7_LUT:u0.port0
oSEG0[3] <= SEG7_LUT:u0.port0
oSEG0[4] <= SEG7_LUT:u0.port0
oSEG0[5] <= SEG7_LUT:u0.port0
oSEG0[6] <= SEG7_LUT:u0.port0
oSEG1[0] <= SEG7_LUT:u1.port0
oSEG1[1] <= SEG7_LUT:u1.port0
oSEG1[2] <= SEG7_LUT:u1.port0
oSEG1[3] <= SEG7_LUT:u1.port0
oSEG1[4] <= SEG7_LUT:u1.port0
oSEG1[5] <= SEG7_LUT:u1.port0
oSEG1[6] <= SEG7_LUT:u1.port0
oSEG2[0] <= SEG7_LUT:u2.port0
oSEG2[1] <= SEG7_LUT:u2.port0
oSEG2[2] <= SEG7_LUT:u2.port0
oSEG2[3] <= SEG7_LUT:u2.port0
oSEG2[4] <= SEG7_LUT:u2.port0
oSEG2[5] <= SEG7_LUT:u2.port0
oSEG2[6] <= SEG7_LUT:u2.port0
oSEG3[0] <= SEG7_LUT:u3.port0
oSEG3[1] <= SEG7_LUT:u3.port0
oSEG3[2] <= SEG7_LUT:u3.port0
oSEG3[3] <= SEG7_LUT:u3.port0
oSEG3[4] <= SEG7_LUT:u3.port0
oSEG3[5] <= SEG7_LUT:u3.port0
oSEG3[6] <= SEG7_LUT:u3.port0
oSEG4[0] <= SEG7_LUT:u4.port0
oSEG4[1] <= SEG7_LUT:u4.port0
oSEG4[2] <= SEG7_LUT:u4.port0
oSEG4[3] <= SEG7_LUT:u4.port0
oSEG4[4] <= SEG7_LUT:u4.port0
oSEG4[5] <= SEG7_LUT:u4.port0
oSEG4[6] <= SEG7_LUT:u4.port0
oSEG5[0] <= SEG7_LUT:u5.port0
oSEG5[1] <= SEG7_LUT:u5.port0
oSEG5[2] <= SEG7_LUT:u5.port0
oSEG5[3] <= SEG7_LUT:u5.port0
oSEG5[4] <= SEG7_LUT:u5.port0
oSEG5[5] <= SEG7_LUT:u5.port0
oSEG5[6] <= SEG7_LUT:u5.port0
oSEG6[0] <= SEG7_LUT:u6.port0
oSEG6[1] <= SEG7_LUT:u6.port0
oSEG6[2] <= SEG7_LUT:u6.port0
oSEG6[3] <= SEG7_LUT:u6.port0
oSEG6[4] <= SEG7_LUT:u6.port0
oSEG6[5] <= SEG7_LUT:u6.port0
oSEG6[6] <= SEG7_LUT:u6.port0
oSEG7[0] <= SEG7_LUT:u7.port0
oSEG7[1] <= SEG7_LUT:u7.port0
oSEG7[2] <= SEG7_LUT:u7.port0
oSEG7[3] <= SEG7_LUT:u7.port0
oSEG7[4] <= SEG7_LUT:u7.port0
oSEG7[5] <= SEG7_LUT:u7.port0
oSEG7[6] <= SEG7_LUT:u7.port0
iDIG[0] => iDIG[0]~31.IN1
iDIG[1] => iDIG[1]~30.IN1
iDIG[2] => iDIG[2]~29.IN1
iDIG[3] => iDIG[3]~28.IN1
iDIG[4] => iDIG[4]~27.IN1
iDIG[5] => iDIG[5]~26.IN1
iDIG[6] => iDIG[6]~25.IN1
iDIG[7] => iDIG[7]~24.IN1
iDIG[8] => iDIG[8]~23.IN1
iDIG[9] => iDIG[9]~22.IN1
iDIG[10] => iDIG[10]~21.IN1
iDIG[11] => iDIG[11]~20.IN1
iDIG[12] => iDIG[12]~19.IN1
iDIG[13] => iDIG[13]~18.IN1
iDIG[14] => iDIG[14]~17.IN1
iDIG[15] => iDIG[15]~16.IN1
iDIG[16] => iDIG[16]~15.IN1
iDIG[17] => iDIG[17]~14.IN1
iDIG[18] => iDIG[18]~13.IN1
iDIG[19] => iDIG[19]~12.IN1
iDIG[20] => iDIG[20]~11.IN1
iDIG[21] => iDIG[21]~10.IN1
iDIG[22] => iDIG[22]~9.IN1
iDIG[23] => iDIG[23]~8.IN1
iDIG[24] => iDIG[24]~7.IN1
iDIG[25] => iDIG[25]~6.IN1
iDIG[26] => iDIG[26]~5.IN1
iDIG[27] => iDIG[27]~4.IN1
iDIG[28] => iDIG[28]~3.IN1
iDIG[29] => iDIG[29]~2.IN1
iDIG[30] => iDIG[30]~1.IN1
iDIG[31] => iDIG[31]~0.IN1


|DE2_Default|SEG7_LUT_8:u0|SEG7_LUT:u0
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|DE2_Default|SEG7_LUT_8:u0|SEG7_LUT:u1
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|DE2_Default|SEG7_LUT_8:u0|SEG7_LUT:u2
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|DE2_Default|SEG7_LUT_8:u0|SEG7_LUT:u3
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|DE2_Default|SEG7_LUT_8:u0|SEG7_LUT:u4
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|DE2_Default|SEG7_LUT_8:u0|SEG7_LUT:u5
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|DE2_Default|SEG7_LUT_8:u0|SEG7_LUT:u6
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|DE2_Default|SEG7_LUT_8:u0|SEG7_LUT:u7
oSEG[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder~0.IN3
iDIG[1] => Decoder~0.IN2
iDIG[2] => Decoder~0.IN1
iDIG[3] => Decoder~0.IN0


|DE2_Default|VGA_Controller:u1
iCursor_RGB_EN[0] => oVGA_B~0.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~1.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~2.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~3.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~4.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~5.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~6.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~7.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~8.OUTPUTSELECT
iCursor_RGB_EN[0] => oVGA_B~9.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~0.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~1.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~2.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~3.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~4.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~5.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~6.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~7.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~8.OUTPUTSELECT
iCursor_RGB_EN[1] => oVGA_G~9.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~3.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~4.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~5.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~6.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~7.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~8.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~9.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~10.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~11.OUTPUTSELECT
iCursor_RGB_EN[2] => oVGA_R~12.OUTPUTSELECT
iCursor_RGB_EN[3] => always1~68.IN0
iCursor_X[0] => always1~3.IN1
iCursor_X[0] => add~5.IN13
iCursor_X[0] => add~7.IN13
iCursor_X[1] => always1~4.IN1