|DE2_Default|VGA_OSD_RAM:u2
oRed[0] <= oRed[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[1] <= oRed[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[2] <= oRed[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[3] <= oRed[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[4] <= oRed[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[5] <= oRed[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[6] <= oRed[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[7] <= oRed[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[8] <= oRed[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oRed[9] <= oRed[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[0] <= oGreen[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[1] <= oGreen[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[2] <= oGreen[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[3] <= oGreen[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[4] <= oGreen[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[5] <= oGreen[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[6] <= oGreen[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[7] <= oGreen[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[8] <= oGreen[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oGreen[9] <= oGreen[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[0] <= oBlue[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[1] <= oBlue[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[2] <= oBlue[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[3] <= oBlue[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[4] <= oBlue[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[5] <= oBlue[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[6] <= oBlue[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[7] <= oBlue[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[8] <= oBlue[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
oBlue[9] <= oBlue[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
iVGA_ADDR[0] => ADDR_d[0].DATAIN
iVGA_ADDR[1] => ADDR_d[1].DATAIN
iVGA_ADDR[2] => ADDR_d[2].DATAIN
iVGA_ADDR[3] => iVGA_ADDR[3]~15.IN1
iVGA_ADDR[4] => iVGA_ADDR[4]~14.IN1
iVGA_ADDR[5] => iVGA_ADDR[5]~13.IN1
iVGA_ADDR[6] => iVGA_ADDR[6]~12.IN1
iVGA_ADDR[7] => iVGA_ADDR[7]~11.IN1
iVGA_ADDR[8] => iVGA_ADDR[8]~10.IN1
iVGA_ADDR[9] => iVGA_ADDR[9]~9.IN1
iVGA_ADDR[10] => iVGA_ADDR[10]~8.IN1
iVGA_ADDR[11] => iVGA_ADDR[11]~7.IN1
iVGA_ADDR[12] => iVGA_ADDR[12]~6.IN1
iVGA_ADDR[13] => iVGA_ADDR[13]~5.IN1
iVGA_ADDR[14] => iVGA_ADDR[14]~4.IN1
iVGA_ADDR[15] => iVGA_ADDR[15]~3.IN1
iVGA_ADDR[16] => iVGA_ADDR[16]~2.IN1
iVGA_ADDR[17] => iVGA_ADDR[17]~1.IN1
iVGA_ADDR[18] => iVGA_ADDR[18]~0.IN1
iVGA_CLK => iVGA_CLK~0.IN1
iWR_DATA => iWR_DATA~0.IN1
iWR_ADDR[3] => iWR_ADDR[3]~15.IN1
iWR_ADDR[4] => iWR_ADDR[4]~14.IN1
iWR_ADDR[5] => iWR_ADDR[5]~13.IN1
iWR_ADDR[6] => iWR_ADDR[6]~12.IN1
iWR_ADDR[7] => iWR_ADDR[7]~11.IN1
iWR_ADDR[8] => iWR_ADDR[8]~10.IN1
iWR_ADDR[9] => iWR_ADDR[9]~9.IN1
iWR_ADDR[10] => iWR_ADDR[10]~8.IN1
iWR_ADDR[11] => iWR_ADDR[11]~7.IN1
iWR_ADDR[12] => iWR_ADDR[12]~6.IN1
iWR_ADDR[13] => iWR_ADDR[13]~5.IN1
iWR_ADDR[14] => iWR_ADDR[14]~4.IN1
iWR_ADDR[15] => iWR_ADDR[15]~3.IN1
iWR_ADDR[16] => iWR_ADDR[16]~2.IN1
iWR_ADDR[17] => iWR_ADDR[17]~1.IN1
iWR_ADDR[18] => iWR_ADDR[18]~0.IN1
iWR_EN => iWR_EN~0.IN1
iWR_CLK => iWR_CLK~0.IN1
iON_R[0] => oRed~9.DATAB
iON_R[1] => oRed~8.DATAB
iON_R[2] => oRed~7.DATAB
iON_R[3] => oRed~6.DATAB
iON_R[4] => oRed~5.DATAB
iON_R[5] => oRed~4.DATAB
iON_R[6] => oRed~3.DATAB
iON_R[7] => oRed~2.DATAB
iON_R[8] => oRed~1.DATAB
iON_R[9] => oRed~0.DATAB
iON_G[0] => oGreen~9.DATAB
iON_G[1] => oGreen~8.DATAB
iON_G[2] => oGreen~7.DATAB
iON_G[3] => oGreen~6.DATAB
iON_G[4] => oGreen~5.DATAB
iON_G[5] => oGreen~4.DATAB
iON_G[6] => oGreen~3.DATAB
iON_G[7] => oGreen~2.DATAB
iON_G[8] => oGreen~1.DATAB
iON_G[9] => oGreen~0.DATAB
iON_B[0] => oBlue~9.DATAB
iON_B[1] => oBlue~8.DATAB
iON_B[2] => oBlue~7.DATAB
iON_B[3] => oBlue~6.DATAB
iON_B[4] => oBlue~5.DATAB
iON_B[5] => oBlue~4.DATAB
iON_B[6] => oBlue~3.DATAB
iON_B[7] => oBlue~2.DATAB
iON_B[8] => oBlue~1.DATAB
iON_B[9] => oBlue~0.DATAB
iOFF_R[0] => oRed~9.DATAA
iOFF_R[1] => oRed~8.DATAA
iOFF_R[2] => oRed~7.DATAA
iOFF_R[3] => oRed~6.DATAA
iOFF_R[4] => oRed~5.DATAA
iOFF_R[5] => oRed~4.DATAA
iOFF_R[6] => oRed~3.DATAA
iOFF_R[7] => oRed~2.DATAA
iOFF_R[8] => oRed~1.DATAA
iOFF_R[9] => oRed~0.DATAA
iOFF_G[0] => oGreen~9.DATAA
iOFF_G[1] => oGreen~8.DATAA
iOFF_G[2] => oGreen~7.DATAA
iOFF_G[3] => oGreen~6.DATAA
iOFF_G[4] => oGreen~5.DATAA
iOFF_G[5] => oGreen~4.DATAA
iOFF_G[6] => oGreen~3.DATAA
iOFF_G[7] => oGreen~2.DATAA
iOFF_G[8] => oGreen~1.DATAA
iOFF_G[9] => oGreen~0.DATAA
iOFF_B[0] => oBlue~9.DATAA
iOFF_B[1] => oBlue~8.DATAA
iOFF_B[2] => oBlue~7.DATAA
iOFF_B[3] => oBlue~6.DATAA
iOFF_B[4] => oBlue~5.DATAA
iOFF_B[5] => oBlue~4.DATAA
iOFF_B[6] => oBlue~3.DATAA
iOFF_B[7] => oBlue~2.DATAA
iOFF_B[8] => oBlue~1.DATAA
iOFF_B[9] => oBlue~0.DATAA
iRST_N => oRed[8]~reg0.ACLR
iRST_N => oRed[7]~reg0.ACLR
iRST_N => oRed[6]~reg0.ACLR
iRST_N => oRed[5]~reg0.ACLR
iRST_N => oRed[4]~reg0.ACLR
iRST_N => oRed[3]~reg0.ACLR
iRST_N => oRed[2]~reg0.ACLR
iRST_N => oRed[1]~reg0.ACLR
iRST_N => oRed[0]~reg0.ACLR
iRST_N => oGreen[9]~reg0.ACLR
iRST_N => oGreen[8]~reg0.ACLR
iRST_N => oGreen[7]~reg0.ACLR
iRST_N => oGreen[6]~reg0.ACLR
iRST_N => oGreen[5]~reg0.ACLR
iRST_N => oGreen[4]~reg0.ACLR
iRST_N => oGreen[3]~reg0.ACLR
iRST_N => oGreen[2]~reg0.ACLR
iRST_N => oGreen[1]~reg0.ACLR
iRST_N => oGreen[0]~reg0.ACLR
iRST_N => oBlue[9]~reg0.ACLR
iRST_N => oBlue[8]~reg0.ACLR
iRST_N => oBlue[7]~reg0.ACLR
iRST_N => oBlue[6]~reg0.ACLR
iRST_N => oBlue[5]~reg0.ACLR
iRST_N => oBlue[4]~reg0.ACLR
iRST_N => oBlue[3]~reg0.ACLR
iRST_N => oBlue[2]~reg0.ACLR
iRST_N => oBlue[1]~reg0.ACLR
iRST_N => oBlue[0]~reg0.ACLR
iRST_N => ADDR_d[2].ACLR
iRST_N => ADDR_d[1].ACLR
iRST_N => ADDR_d[0].ACLR
iRST_N => ADDR_dd[2].ACLR
iRST_N => ADDR_dd[1].ACLR
iRST_N => ADDR_dd[0].ACLR
iRST_N => oRed[9]~reg0.ACLR


|DE2_Default|VGA_OSD_RAM:u2|Img_RAM:u0
data[0] => data[0]~0.IN1
wren => wren~0.IN1
wraddress[0] => wraddress[0]~18.IN1
wraddress[1] => wraddress[1]~17.IN1
wraddress[2] => wraddress[2]~16.IN1
wraddress[3] => wraddress[3]~15.IN1
wraddress[4] => wraddress[4]~14.IN1
wraddress[5] => wraddress[5]~13.IN1
wraddress[6] => wraddress[6]~12.IN1
wraddress[7] => wraddress[7]~11.IN1
wraddress[8] => wraddress[8]~10.IN1
wraddress[9] => wraddress[9]~9.IN1
wraddress[10] => wraddress[10]~8.IN1
wraddress[11] => wraddress[11]~7.IN1
wraddress[12] => wraddress[12]~6.IN1
wraddress[13] => wraddress[13]~5.IN1
wraddress[14] => wraddress[14]~4.IN1
wraddress[15] => wraddress[15]~3.IN1
wraddress[16] => wraddress[16]~2.IN1
wraddress[17] => wraddress[17]~1.IN1
wraddress[18] => wraddress[18]~0.IN1
rdaddress[0] => rdaddress[0]~15.IN1
rdaddress[1] => rdaddress[1]~14.IN1
rdaddress[2] => rdaddress[2]~13.IN1
rdaddress[3] => rdaddress[3]~12.IN1
rdaddress[4] => rdaddress[4]~11.IN1
rdaddress[5] => rdaddress[5]~10.IN1
rdaddress[6] => rdaddress[6]~9.IN1
rdaddress[7] => rdaddress[7]~8.IN1
rdaddress[8] => rdaddress[8]~7.IN1
rdaddress[9] => rdaddress[9]~6.IN1
rdaddress[10] => rdaddress[10]~5.IN1
rdaddress[11] => rdaddress[11]~4.IN1
rdaddress[12] => rdaddress[12]~3.IN1
rdaddress[13] => rdaddress[13]~2.IN1
rdaddress[14] => rdaddress[14]~1.IN1
rdaddress[15] => rdaddress[15]~0.IN1
wrclock => wrclock~0.IN1
rdclock => rdclock~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b


|DE2_Default|VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component
wren_a => altsyncram_e3f1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_e3f1:auto_generated.data_a[0]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_e3f1:auto_generated.address_a[0]
address_a[1] => altsyncram_e3f1:auto_generated.address_a[1]
address_a[2] => altsyncram_e3f1:auto_generated.address_a[2]
address_a[3] => altsyncram_e3f1:auto_generated.address_a[3]
address_a[4] => altsyncram_e3f1:auto_generated.address_a[4]
address_a[5] => altsyncram_e3f1:auto_generated.address_a[5]
address_a[6] => altsyncram_e3f1:auto_generated.address_a[6]
address_a[7] => altsyncram_e3f1:auto_generated.address_a[7]
address_a[8] => altsyncram_e3f1:auto_generated.address_a[8]
address_a[9] => altsyncram_e3f1:auto_generated.address_a[9]
address_a[10] => altsyncram_e3f1:auto_generated.address_a[10]
address_a[11] => altsyncram_e3f1:auto_generated.address_a[11]
address_a[12] => altsyncram_e3f1:auto_generated.address_a[12]
address_a[13] => altsyncram_e3f1:auto_generated.address_a[13]
address_a[14] => altsyncram_e3f1:auto_generated.address_a[14]
address_a[15] => altsyncram_e3f1:auto_generated.address_a[15]
address_a[16] => altsyncram_e3f1:auto_generated.address_a[16]
address_a[17] => altsyncram_e3f1:auto_generated.address_a[17]
address_a[18] => altsyncram_e3f1:auto_generated.address_a[18]
address_b[0] => altsyncram_e3f1:auto_generated.address_b[0]
address_b[1] => altsyncram_e3f1:auto_generated.address_b[1]
address_b[2] => altsyncram_e3f1:auto_generated.address_b[2]
address_b[3] => altsyncram_e3f1:auto_generated.address_b[3]
address_b[4] => altsyncram_e3f1:auto_generated.address_b[4]
address_b[5] => altsyncram_e3f1:auto_generated.address_b[5]
address_b[6] => altsyncram_e3f1:auto_generated.address_b[6]
address_b[7] => altsyncram_e3f1:auto_generated.address_b[7]
address_b[8] => altsyncram_e3f1:auto_generated.address_b[8]
address_b[9] => altsyncram_e3f1:auto_generated.address_b[9]
address_b[10] => altsyncram_e3f1:auto_generated.address_b[10]
address_b[11] => altsyncram_e3f1:auto_generated.address_b[11]
address_b[12] => altsyncram_e3f1:auto_generated.address_b[12]
address_b[13] => altsyncram_e3f1:auto_generated.address_b[13]
address_b[14] => altsyncram_e3f1:auto_generated.address_b[14]
address_b[15] => altsyncram_e3f1:auto_generated.address_b[15]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_e3f1:auto_generated.clock0
clock1 => altsyncram_e3f1:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_b[0] <= altsyncram_e3f1:auto_generated.q_b[0]
q_b[1] <= altsyncram_e3f1:auto_generated.q_b[1]
q_b[2] <= altsyncram_e3f1:auto_generated.q_b[2]
q_b[3] <= altsyncram_e3f1:auto_generated.q_b[3]
q_b[4] <= altsyncram_e3f1:auto_generated.q_b[4]
q_b[5] <= altsyncram_e3f1:auto_generated.q_b[5]
q_b[6] <= altsyncram_e3f1:auto_generated.q_b[6]
q_b[7] <= altsyncram_e3f1:auto_generated.q_b[7]


|DE2_Default|VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated
address_a[0] => altsyncram_8en1:altsyncram1.address_b[0]
address_a[1] => altsyncram_8en1:altsyncram1.address_b[1]
address_a[2] => altsyncram_8en1:altsyncram1.address_b[2]
address_a[3] => altsyncram_8en1:altsyncram1.address_b[3]
address_a[4] => altsyncram_8en1:altsyncram1.address_b[4]
address_a[5] => altsyncram_8en1:altsyncram1.address_b[5]
address_a[6] => altsyncram_8en1:altsyncram1.address_b[6]
address_a[7] => altsyncram_8en1:altsyncram1.address_b[7]
address_a[8] => altsyncram_8en1:altsyncram1.address_b[8]
address_a[9] => altsyncram_8en1:altsyncram1.address_b[9]
address_a[10] => altsyncram_8en1:altsyncram1.address_b[10]
address_a[11] => altsyncram_8en1:altsyncram1.address_b[11]
address_a[12] => altsyncram_8en1:altsyncram1.address_b[12]
address_a[13] => altsyncram_8en1:altsyncram1.address_b[13]
address_a[14] => altsyncram_8en1:altsyncram1.address_b[14]
address_a[15] => altsyncram_8en1:altsyncram1.address_b[15]
address_a[16] => altsyncram_8en1:altsyncram1.address_b[16]
address_a[17] => altsyncram_8en1:altsyncram1.address_b[17]
address_a[18] => altsyncram_8en1:altsyncram1.address_b[18]
address_b[0] => altsyncram_8en1:altsyncram1.address_a[0]
address_b[1] => altsyncram_8en1:altsyncram1.address_a[1]
address_b[2] => altsyncram_8en1:altsyncram1.address_a[2]
address_b[3] => altsyncram_8en1:altsyncram1.address_a[3]
address_b[4] => altsyncram_8en1:altsyncram1.address_a[4]
address_b[5] => altsyncram_8en1:altsyncram1.address_a[5]
address_b[6] => altsyncram_8en1:altsyncram1.address_a[6]
address_b[7] => altsyncram_8en1:altsyncram1.address_a[7]
address_b[8] => altsyncram_8en1:altsyncram1.address_a[8]
address_b[9] => altsyncram_8en1:altsyncram1.address_a[9]
address_b[10] => altsyncram_8en1:altsyncram1.address_a[10]
address_b[11] => altsyncram_8en1:altsyncram1.address_a[11]
address_b[12] => altsyncram_8en1:altsyncram1.address_a[12]
address_b[13] => altsyncram_8en1:altsyncram1.address_a[13]
address_b[14] => altsyncram_8en1:altsyncram1.address_a[14]
address_b[15] => altsyncram_8en1:altsyncram1.address_a[15]
clock0 => altsyncram_8en1:altsyncram1.clock1
clock1 => altsyncram_8en1:altsyncram1.clock0
data_a[0] => altsyncram_8en1:altsyncram1.data_b[0]
q_b[0] <= altsyncram_8en1:altsyncram1.q_a[0]
q_b[1] <= altsyncram_8en1:altsyncram1.q_a[1]
q_b[2] <= altsyncram_8en1:altsyncram1.q_a[2]
q_b[3] <= altsyncram_8en1:altsyncram1.q_a[3]
q_b[4] <= altsyncram_8en1:altsyncram1.q_a[4]
q_b[5] <= altsyncram_8en1:altsyncram1.q_a[5]
q_b[6] <= altsyncram_8en1:altsyncram1.q_a[6]
q_b[7] <= altsyncram_8en1:altsyncram1.q_a[7]
wren_a => altsyncram_8en1:altsyncram1.wren_b


|DE2_Default|VGA_OSD_RAM:u2|Img_RAM:u0|altsyncram:altsyncram_component|altsyncram_e3f1:auto_generated|altsyncram_8en1:altsyncram1
address_a[0] => ram_block2a0.PORTAADDR
address_a[0] => ram_block2a1.PORTAADDR
address_a[0] => ram_block2a2.PORTAADDR
address_a[0] => ram_block2a3.PORTAADDR
address_a[0] => ram_block2a4.PORTAADDR
address_a[0] => ram_block2a5.PORTAADDR
address_a[0] => ram_block2a6.PORTAADDR
address_a[0] => ram_block2a7.PORTAADDR
address_a[0] => ram_block2a8.PORTAADDR
address_a[0] => ram_block2a9.PORTAADDR
address_a[0] => ram_block2a10.PORTAADDR
address_a[0] => ram_block2a11.PORTAADDR
address_a[0] => ram_block2a12.PORTAADDR
address_a[0] => ram_block2a13.PORTAADDR
address_a[0] => ram_block2a14.PORTAADDR
address_a[0] => ram_block2a15.PORTAADDR
address_a[0] => ram_block2a16.PORTAADDR
address_a[0] => ram_block2a17.PORTAADDR
address_a[0] => ram_block2a18.PORTAADDR
address_a[0] => ram_block2a19.PORTAADDR
address_a[0] => ram_block2a20.PORTAADDR
address_a[0] => ram_block2a21.PORTAADDR
address_a[0] => ram_block2a22.PORTAADDR
address_a[0] => ram_block2a23.PORTAADDR
address_a[0] => ram_block2a24.PORTAADDR
address_a[0] => ram_block2a25.PORTAADDR
address_a[0] => ram_block2a26.PORTAADDR
address_a[0] => ram_block2a27.PORTAADDR
address_a[0] => ram_block2a28.PORTAADDR
address_a[0] => ram_block2a29.PORTAADDR
address_a[0] => ram_block2a30.PORTAADDR
address_a[0] => ram_block2a31.PORTAADDR
address_a[0] => ram_block2a32.PORTAADDR
address_a[0] => ram_block2a33.PORTAADDR