; Allow Any ROM Size For Recognition                                                         ; Off          ; Off           ;
; Allow Any Shift Register Size For Recognition                                              ; Off          ; Off           ;
; Ignore translate_off and translate_on Synthesis Directives                                 ; Off          ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                                         ; On           ; On            ;
+--------------------------------------------------------------------------------------------+--------------+---------------+


+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                    ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+
; cam.vhd                          ; yes             ; User VHDL File  ; C:/Documents and Settings/yoyo/桌面/CAM/cam.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 113       ;
; Total combinational functions   ; 77        ;
;     -- Total 4-input functions  ; 61        ;
;     -- Total 3-input functions  ; 12        ;
;     -- Total 2-input functions  ; 3         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 1         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 47        ;
; I/O pins                        ; 26        ;
; Maximum fan-out node            ; clk       ;
; Maximum fan-out                 ; 47        ;
; Total fan-out                   ; 473       ;
; Average fan-out                 ; 3.40      ;
+---------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |cam                       ; 113 (113)   ; 47           ; 0           ; 26   ; 0            ; 66 (66)      ; 36 (36)           ; 11 (11)          ; 0 (0)           ; |cam                ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 47    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 45    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 44    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |cam ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type                                       ;
+----------------+-------+--------------------------------------------+
; camwidthin     ; 8     ; Integer                                    ;
; camwidthout    ; 2     ; Integer                                    ;
; camdepth       ; 4     ; Integer                                    ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/yoyo/桌面/CAM/cam.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Nov 18 16:52:03 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cam -c cam
Info: Found 2 design units, including 1 entities, in source file cam.vhd
    Info: Found design unit 1: cam-behavioural
    Info: Found entity 1: cam
Info: Elaborating entity "cam" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at cam.vhd(57): object "addr" declared but not used
Info: Implemented 139 device resources after synthesis - the final resource count might be different
    Info: Implemented 22 input pins
    Info: Implemented 4 output pins
    Info: Implemented 113 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Nov 18 16:52:06 2005
    Info: Elapsed time: 00:00:03