library ieee;
use ieee.std_logic_1164.all;

entity div3 is
port(clk:std_logic;
     f,f1,f2,f6:out std_logic);
end div3;

architecture behavioral of div3 is
signal count1,count2,count3,count4:integer range 0 to 3;
signal f3,f4,f5,f7,f8:std_logic;
begin
  process(clk)--上升沿3分頻
   begin
    if (count1=3)then count1<=0;f3<='0';
    elsif (clk'event and clk='1')then
    count1<=count1+1;
    f3<='1';
    end if;
  end process;
  process(clk)--下降沿3分頻
   begin
   if (count2=3)then count2<=0;f4<='0';
    elsif (clk'event and clk='0')then
    count2<=count2+1;
    f4<='1';
    end if;
  end process;

 process(f5)--上升沿3分頻
   begin
    if (count3=3)then count3<=0;f7<='0';
    elsif (f5'event and f5='1')then
    count3<=count3+1;
    f7<='1';
    end if;
  end process;
  process(f5)--下降沿3分頻
   begin
   if (count4=3)then count4<=0;f8<='0';
    elsif (f5'event and f5='0')then
    count4<=count4+1;
    f8<='1';
    end if;
  end process;


 f1<=f3;
 f2<=f4;
 f5<=f3 and f4;--3分頻50%占空比
 f<=f5;
 f6<=f7 and f8;
end behavioral;