?? div3.tan.rpt
字號:
Timing Analyzer report for div3
Wed Sep 20 21:54:00 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-----------+-----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-----------+-----------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 9.473 ns ; f8 ; f6 ; clk ; ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count4[0] ; count4[1] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-----------+-----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T100C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count4[0] ; count4[1] ; clk ; clk ; None ; None ; 1.114 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count3[0] ; count3[1] ; clk ; clk ; None ; None ; 1.102 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count1[0] ; count1[1] ; clk ; clk ; None ; None ; 1.113 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count2[0] ; count2[1] ; clk ; clk ; None ; None ; 1.102 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count4[0] ; count4[0] ; clk ; clk ; None ; None ; 0.796 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count3[0] ; count3[0] ; clk ; clk ; None ; None ; 0.787 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count1[0] ; count1[0] ; clk ; clk ; None ; None ; 0.796 ns ;
; N/A ; Restricted to 405.19 MHz ( period = 2.468 ns ) ; count2[0] ; count2[0] ; clk ; clk ; None ; None ; 0.787 ns ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+----+------------+
; N/A ; None ; 9.473 ns ; f8 ; f6 ; clk ;
; N/A ; None ; 9.321 ns ; f7 ; f6 ; clk ;
; N/A ; None ; 5.914 ns ; f4 ; f ; clk ;
; N/A ; None ; 5.759 ns ; f3 ; f ; clk ;
; N/A ; None ; 5.601 ns ; f4 ; f2 ; clk ;
; N/A ; None ; 5.262 ns ; f3 ; f1 ; clk ;
+-------+--------------+------------+------+----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Sep 20 21:53:59 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div3 -c div3 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "f5~0" as buffer
Info: Detected ripple clock "f4" as buffer
Info: Detected ripple clock "f3" as buffer
Info: Clock "clk" Internal fmax is restricted to 405.19 MHz between source register "count4[0]" and destination register "count4[1]"
Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.114 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y6_N2; Fanout = 3; REG Node = 'count4[0]'
Info: 2: + IC(0.447 ns) + CELL(0.667 ns) = 1.114 ns; Loc. = LC_X26_Y6_N5; Fanout = 1; REG Node = 'count4[1]'
Info: Total cell delay = 0.667 ns ( 59.87 % )
Info: Total interconnect delay = 0.447 ns ( 40.13 % )
Info: - Smallest clock skew is -0.155 ns
Info: + Shortest clock path from clock "clk" to destination register is 5.967 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N0; Fanout = 2; REG Node = 'f3'
Info: 3: + IC(0.395 ns) + CELL(0.088 ns) = 2.762 ns; Loc. = LC_X8_Y6_N2; Fanout = 7; COMB Node = 'f5~0'
Info: 4: + IC(2.658 ns) + CELL(0.547 ns) = 5.967 ns; Loc. = LC_X26_Y6_N5; Fanout = 1; REG Node = 'count4[1]'
Info: Total cell delay = 2.485 ns ( 41.65 % )
Info: Total interconnect delay = 3.482 ns ( 58.35 % )
Info: - Longest clock path from clock "clk" to source register is 6.122 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N9; Fanout = 2; REG Node = 'f4'
Info: 3: + IC(0.413 ns) + CELL(0.225 ns) = 2.917 ns; Loc. = LC_X8_Y6_N2; Fanout = 7; COMB Node = 'f5~0'
Info: 4: + IC(2.658 ns) + CELL(0.547 ns) = 6.122 ns; Loc. = LC_X26_Y6_N2; Fanout = 3; REG Node = 'count4[0]'
Info: Total cell delay = 2.622 ns ( 42.83 % )
Info: Total interconnect delay = 3.500 ns ( 57.17 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Micro setup delay of destination is 0.029 ns
Info: tco from clock "clk" to destination pin "f6" through register "f8" is 9.473 ns
Info: + Longest clock path from clock "clk" to source register is 6.092 ns
Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 6; CLK Node = 'clk'
Info: 2: + IC(0.429 ns) + CELL(0.720 ns) = 2.279 ns; Loc. = LC_X8_Y6_N9; Fanout = 2; REG Node = 'f4'
Info: 3: + IC(0.413 ns) + CELL(0.225 ns) = 2.917 ns; Loc. = LC_X8_Y6_N2; Fanout = 7; COMB Node = 'f5~0'
Info: 4: + IC(2.628 ns) + CELL(0.547 ns) = 6.092 ns; Loc. = LC_X22_Y1_N2; Fanout = 1; REG Node = 'f8'
Info: Total cell delay = 2.622 ns ( 43.04 % )
Info: Total interconnect delay = 3.470 ns ( 56.96 % )
Info: + Micro clock to output delay of source is 0.173 ns
Info: + Longest register to pin delay is 3.208 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X22_Y1_N2; Fanout = 1; REG Node = 'f8'
Info: 2: + IC(0.412 ns) + CELL(0.225 ns) = 0.637 ns; Loc. = LC_X22_Y1_N4; Fanout = 1; COMB Node = 'f6~0'
Info: 3: + IC(0.949 ns) + CELL(1.622 ns) = 3.208 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'f6'
Info: Total cell delay = 1.847 ns ( 57.57 % )
Info: Total interconnect delay = 1.361 ns ( 42.43 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Wed Sep 20 21:54:00 2006
Info: Elapsed time: 00:00:02
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -