//******************////copyright 2007, DTK//all right reserved////project name: : project_first//filename    : file_first//author      : wangyang//data        : 2007/8/1//version     : 1.0////module name : module_fisrt//abstract     : this is my first coding_test in dtk////modification history//---------------------------------//&Log&////*************************module first(Clk,Rst_,Data_In,Data_Delay_1Reg,Data_Delay_2Reg);input Clk;input Rst_;input Data_In;output Data_Delay_1Reg;output Data_Delay_2Reg;wire Clk;wire Rst_;wire Data_In;reg Data_Delay_1Reg;reg Data_Delay_2Reg;always @( posedge Clk ) begin : TIME_DELAYif ( !Rst_) beginData_Delay_2Reg <= 1'b0;Data_Delay_1Reg <= 1'b0;end			//to delay data_in two clock time, to fix  first module timing;else beginData_Delay_2Reg <= Data_Delay_1Reg;Data_Delay_1Reg <= Data_In;endendendmodule