//******************////copyright 2007, DTK//all right reserved////project name: : test9//filename    : file_I/O_design//author      : wangyang//data        : 2007/8/3//version     : 1.0////module name : module_writing//abstract     : ???????????////modification history//---------------------------------//&Log&//******************module writing(Reset,Clk,Address,Data,Sda,Ack);  input Reset,Clk;  input[7:0] Data,Address;    output Sda,Ack;//sda????????                 //ack????????????  reg Link_Write;//link_write ???????  reg[3:0] State;//????????  reg[4:0] Sh8out_State;//????????  reg[7:0] Sh8out_Buf;    //??????  reg Finish_F;           //???????????????  reg Ack;    parameter    Idle=0,Addr_Write=1,Data_Write=2,Stop_Ack=3;  parameter    Bit0=1,Bit1=2,Bit2=3,Bit3=4,Bit4=5,Bit5=6,Bit6=7,Bit7=8;     assign   Sda = Link_Write? Sh8out_Buf[7] : 1'bz;    always @(posedge Clk)    begin    	if(!Reset)               //??    	  begin    	  	 Link_Write<= 0;      //???????    	  	 State    <= Idle;        	  	 Finish_F <= 0;       //??????    	  	 Sh8out_State<=Idle;    	  	       Ack<= 0;    	  	 Sh8out_Buf<=0;    	  end    	else    	  case(State)    	      	  Idle:                           	    begin    	    	Link_Write  <= 0;     //???????    	  	   State    <= Idle;    	  	   Finish_F <= 0;    	  	   Sh8out_State<=Idle;    	  	         Ack<= 0;    	  	   Sh8out_Buf<=Address;  //?????????    	      State    <= Addr_Write;//???????    	    end    	      	  Addr_Write:         //???????    	    begin    	    	if(Finish_F==0)    	    	  begin      	    	    Shift8_Out;     	    	  end    	    	else    	    	  begin    	    	  	 Sh8out_State <= Idle;    	    	  	 Sh8out_Buf   <= Data;//?????????   	    	  	         State <= Data_Write;    	    	  	    Finish_F <= 0;    	    	  end    	    end    	      	  Data_Write:       //?????    	    begin    	    	if(Finish_F==0)     	    	  begin      	    	    Shift8_Out; //???????(task??)    	    	  end    	    	else    	    	  begin    	    	  	  Link_Write <= 0;    	    	  	       State <= Stop_Ack;    	    	  	    Finish_F <= 0;      	    	  	         Ack <= 1;    	    	  end    	    end 	    	      	  Stop_Ack:             //??????????    	    begin    	    	  Ack <= 0;    	      State <= Idle;    	    end    	      	  endcase           end 	      	                  	    	   task Shift8_Out;                //??????????  begin  	 case(Sh8out_State)  	   	 Idle:   	   begin  	 	   Link_Write  <= 1;  	 	  Sh8out_State <= Bit0;  	 	end  	   	 Bit0:  	   begin  	       Link_Write <= 1;  	       Sh8out_State <= Bit1; 	          	  	                  	       Sh8out_Buf <= Sh8out_Buf<<1;  	   end  	   	 Bit1:  	   begin  	     Sh8out_State<=Bit2;  	     Sh8out_Buf<=Sh8out_Buf<<1;  	   end  	     	 Bit2:  	   begin  	     Sh8out_State<=Bit3;  	     Sh8out_Buf<=Sh8out_Buf<<1;  	   end  	   	 Bit3:  	   begin  	     Sh8out_State<=Bit4;  	     Sh8out_Buf<=Sh8out_Buf<<1;  	   end  	   	 Bit4:  	   begin  	     Sh8out_State<=Bit5;  	     Sh8out_Buf<=Sh8out_Buf<<1;  	   end  	   	 Bit5:  	   begin  	     Sh8out_State<=Bit6;  	     Sh8out_Buf<=Sh8out_Buf<<1;  	   end  	   	 Bit6:  	   begin  	     Sh8out_State<=Bit7;  	     Sh8out_Buf<=Sh8out_Buf<<1;  	   end  	   	 Bit7:  	   begin  	     Link_Write<= 0;  	     Finish_F<=Finish_F+1;           	                    	   end    	     	 endcase  endendtaskendmodule   	   //????????`timescale 1ns/100ps`define clk_cycle 50module writing_test;  reg Reset,Clk;  reg[7:0] Data,Address;  wire Ack,Sda;    always #`clk_cycle  Clk = ~Clk;    initial    begin    		Clk=0;    		Reset=1;    		Data=0;    		Address=0;    		#(2*`clk_cycle) Reset=0;    		#(2*`clk_cycle) Reset=1;   	 	#(100*`clk_cycle) $stop;    end      always @(posedge Ack)      //???????????????????    begin    		Data=Data+1;    		Address=Address+1;    end 	  	  writing writing(.Reset(Reset),.Clk(Clk),.Data(Data),                  .Address(Address),.Ack(Ack),.Sda(Sda));  endmodule