//******************////copyright 2007, DTK//all right reserved////project name: : squence_detective//filename    : file_module_seqdet//author      : wangyang//data        : 2007/8/4//version     : 1.0////module name : module_seqdet//abstract     : detective "10010" suqence////modification history//---------------------------------//&Log&//******************module seqdet(X,Z,Clk,Rst);    input X;    input Clk;    input Rst;    output Z;        reg [2:0] state;    wire Z;        parameter Idle=3'd0,              A=3'd1,              B=3'd2,              C=3'd3,              D=3'd4,              E=3'd5,              F=3'd6,              G=3'd7;                  assign Z=(state==E&&X==0)?1:0;        always@(posedge Clk or negedge Rst)    if(!Rst)    begin        state<=Idle;    end    else    case(state)        Idle:if(X==1)             state<=A;             else state<=Idle;        A:   if(X==0)             state<=B;             else state<=A;        B:   if(X==0)             state<=C;             else state<=F;        C:   if(X==1)             state<=D;             else state<=G;        D:   if(X==0)             state<=E;             else state<=A;        E:   if(X==0)             state<=C;             else state<=A;        F:   if(X==1)             state<=A;             else             state<=B;        G:   if(X==1)             state<=F;             else state<=G;            default: state<=Idle;endcaseendmodule//test program`timescale 1ns/1nsmodule t;    reg Clk;    reg Rst;    reg [23:0] data;    wire Z;    wire X;    assign X=data[23];        always #10 Clk=~Clk;    always@(posedge Clk)    data={data[22:0],data[23]};        initial    begin        Clk=0;        Rst=1;        #2 Rst=0;        #30 Rst=1;        data=20'b1100_1001_0000_1001_0100;        #100000 $stop;    end            seqdet m(.X(X),.Z(Z),.Clk(Clk),.Rst(Rst));endmodule