library ieee;   use ieee.std_logic_1164.all;   use ieee.numeric_std.all;--------------------------------------------------------------------------------- Baud rate generator-------------------------------------------------------------------------------entity SEL is  port (     RBuffer  : in  std_logic_vector(7 DOWNTO 0);  -- System Clock     DReady   : in  Std_Logic;     Rst      : in  Std_Logic;     Servo_Width_Ctr   :OUT std_logic_vector(6 DOWNTO 0);      Motor_Width_Ctr   : OUT std_logic_vector(6 DOWNTO 0)); end entity; --================== End of entity ==============================----------------------------------------------------------------------------------- Architecture for Baud rate generator Unit-------------------------------------------------------------------------------architecture Behaviour of SEL is  -----------------------------------------------------------------------------  -- Signals  -----------------------------------------------------------------------------beginPROCESS(Rst,DReady)BEGINIF Rst ='0' THENServo_Width_Ctr<="0111111";Motor_Width_Ctr<="0111111";ELSIF DReady='1' THEN    IF RBuffer(7)='1' THEN    Servo_Width_Ctr<=RBuffer(6 DOWNTO 0);    ELSE Motor_Width_Ctr<=RBuffer(6 DOWNTO 0);    END IF;END IF;END PROCESS;end Behaviour; --==================== End of architecture ===================--