Fitter report for test
Fri Sep 21 20:01:17 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Pin-Out File
  5. Fitter Resource Usage Summary
  6. Input Pins
  7. Output Pins
  8. I/O Bank Usage
  9. All Package Pins
 10. Output Pin Default Load For Reported TCO
 11. Fitter Resource Utilization by Entity
 12. Delay Chain Summary
 13. Control Signals
 14. Global & Other Fast Signals
 15. Non-Global High Fan-Out Signals
 16. Interconnect Usage Summary
 17. LAB Logic Elements
 18. LAB-wide Signals
 19. LAB Signals Sourced
 20. LAB Signals Sourced Out
 21. LAB Distinct Inputs
 22. Fitter Device Options
 23. Fitter Messages
 24. Fitter Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Fri Sep 21 20:01:17 2007    ;
; Quartus II Version    ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name         ; test                                     ;
; Top-level Entity Name ; test                                     ;
; Family                ; MAX II                                   ;
; Device                ; EPM1270T144C5                            ;
; Timing Models         ; Final                                    ;
; Total logic elements  ; 159 / 1,270 ( 13 % )                     ;
; Total pins            ; 5 / 116 ( 4 % )                          ;
; Total virtual pins    ; 0                                        ;
; UFM blocks            ; 0 / 1 ( 0 % )                            ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                          ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                 ; Setting                        ; Default Value                  ;
+--------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                 ; EPM1270T144C5                  ;                                ;
; Use smart compilation                                  ; Off                            ; Off                            ;
; Router Timing Optimization Level                       ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                            ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                               ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                   ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                            ; Off                            ; Off                            ;
; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On                             ; On                             ;
; PowerPlay Power Optimization                           ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; Slow Slew Rate                                         ; Off                            ; Off                            ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;
; Fitter Effort                                          ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication               ; Auto                           ; Auto                           ;
; Auto Register Duplication                              ; Auto                           ; Auto                           ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Always Enable Input Buffers                            ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/test.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 159 / 1,270 ( 13 % ) ;
;     -- Combinational with no register       ; 99                   ;
;     -- Register only                        ; 7                    ;
;     -- Combinational with a register        ; 53                   ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 60                   ;
;     -- 3 input functions                    ; 27                   ;
;     -- 2 input functions                    ; 59                   ;
;     -- 1 input functions                    ; 7                    ;
;     -- 0 input functions                    ; 6                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 116                  ;
;     -- arithmetic mode                      ; 43                   ;
;     -- qfbk mode                            ; 5                    ;
;     -- register cascade mode                ; 0                    ;
;     -- synchronous clear/load mode          ; 14                   ;
;     -- asynchronous clear/load mode         ; 0                    ;
;                                             ;                      ;
; Total LABs                                  ; 19 / 127 ( 15 % )    ;
; Logic elements in carry chains              ; 49                   ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 5 / 116 ( 4 % )      ;
;     -- Clock pins                           ; 0 / 0 ( -- )         ;
; Global signals                              ; 4                    ;
; UFM blocks                                  ; 0 / 1 ( 0 % )        ;
; Global clocks                               ; 4 / 4 ( 100 % )      ;
; Maximum fan-out node                        ; rst                  ;
; Maximum fan-out                             ; 54                   ;
; Highest non-global fan-out signal           ; rst                  ;
; Highest non-global fan-out                  ; 54                   ;
; Total fan-out                               ; 551                  ;
; Average fan-out                             ; 3.36                 ;
+---------------------------------------------+----------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                  ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; clk  ; 127   ; 2        ; 9            ; 11           ; 3           ; 46                    ; 0                  ; yes    ; no              ; no       ; Off          ; LVTTL        ; User                 ;
; rst  ; 110   ; 2        ; 16           ; 11           ; 2           ; 54                    ; 0                  ; no     ; no              ; no       ; Off          ; LVTTL        ; User                 ;
; rxd  ; 77    ; 3        ; 17           ; 2            ; 0           ; 3                     ; 0                  ; no     ; no              ; no       ; Off          ; LVTTL        ; User                 ;