?? test.fit.rpt
字號(hào):
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 12 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 0.74) ; Number of LABs (Total = 19) ;
+------------------------------------+------------------------------+
; 1 Clock ; 13 ;
; 1 Sync. clear ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 7.95) ; Number of LABs (Total = 19) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 4 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.16) ; Number of LABs (Total = 19) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 1 ;
; 6 ; 4 ;
; 7 ; 3 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 8.95) ; Number of LABs (Total = 19) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 3 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 3 ;
; 8 ; 4 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 1 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 2 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Sep 21 20:01:14 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off test -c test
Info: Selected device EPM1270T144C5 for design "test"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock
Info: Pin "clk" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted some destinations of signal "PWM:inst3|clk_servo" to use Global clock
Info: Destination "PWM:inst3|clk_servo" may be non-global or may not use global clock
Info: Automatically promoted signal "SEL:inst2|comb~0" to use Global clock
Info: Automatically promoted signal "SEL:inst2|comb~1" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 5.428 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y8; Fanout = 1; REG Node = 'PWM:inst3|to_servo'
Info: 2: + IC(3.106 ns) + CELL(2.322 ns) = 5.428 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'to_servo'
Info: Total cell delay = 2.322 ns ( 42.78 % )
Info: Total interconnect delay = 3.106 ns ( 57.22 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 5%
Info: The peak interconnect region extends from location x9_y0 to location x17_y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Sep 21 20:01:17 2007
Info: Elapsed time: 00:00:04
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/test.fit.smsg.
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