{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 45 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register SampleCnt\[3\] register ShtReg\[6\] 111.77 MHz 8.947 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 111.77 MHz between source register \"SampleCnt\[3\]\" and destination register \"ShtReg\[6\]\" (period= 8.947 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.238 ns + Longest register register " "Info: + Longest register to register delay is 8.238 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SampleCnt\[3\] 1 REG LC_X11_Y6_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y6_N3; Fanout = 3; REG Node = 'SampleCnt\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SampleCnt[3] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.908 ns) + CELL(0.914 ns) 2.822 ns Equal1~35 2 COMB LC_X9_Y6_N1 6 " "Info: 2: + IC(1.908 ns) + CELL(0.914 ns) = 2.822 ns; Loc. = LC_X9_Y6_N1; Fanout = 6; COMB Node = 'Equal1~35'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.822 ns" { SampleCnt[3] Equal1~35 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.799 ns) + CELL(0.200 ns) 4.821 ns ShtReg\[0\]~569 3 COMB LC_X10_Y6_N6 1 " "Info: 3: + IC(1.799 ns) + CELL(0.200 ns) = 4.821 ns; Loc. = LC_X10_Y6_N6; Fanout = 1; COMB Node = 'ShtReg\[0\]~569'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.999 ns" { Equal1~35 ShtReg[0]~569 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.326 ns ShtReg\[0\]~570 4 COMB LC_X10_Y6_N7 8 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.326 ns; Loc. = LC_X10_Y6_N7; Fanout = 8; COMB Node = 'ShtReg\[0\]~570'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { ShtReg[0]~569 ShtReg[0]~570 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.669 ns) + CELL(1.243 ns) 8.238 ns ShtReg\[6\] 5 REG LC_X7_Y6_N4 1 " "Info: 5: + IC(1.669 ns) + CELL(1.243 ns) = 8.238 ns; Loc. = LC_X7_Y6_N4; Fanout = 1; REG Node = 'ShtReg\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.912 ns" { ShtReg[0]~570 ShtReg[6] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.557 ns ( 31.04 % ) " "Info: Total cell delay = 2.557 ns ( 31.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.681 ns ( 68.96 % ) " "Info: Total interconnect delay = 5.681 ns ( 68.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.238 ns" { SampleCnt[3] Equal1~35 ShtReg[0]~569 ShtReg[0]~570 ShtReg[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.238 ns" { SampleCnt[3] Equal1~35 ShtReg[0]~569 ShtReg[0]~570 ShtReg[6] } { 0.000ns 1.908ns 1.799ns 0.305ns 1.669ns } { 0.000ns 0.914ns 0.200ns 0.200ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 7.334 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 7.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Clk 1 CLK PIN_127 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 29; CLK Node = 'Clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.284 ns) + CELL(0.918 ns) 7.334 ns ShtReg\[6\] 2 REG LC_X7_Y6_N4 1 " "Info: 2: + IC(5.284 ns) + CELL(0.918 ns) = 7.334 ns; Loc. = LC_X7_Y6_N4; Fanout = 1; REG Node = 'ShtReg\[6\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.202 ns" { Clk ShtReg[6] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.95 % ) " "Info: Total cell delay = 2.050 ns ( 27.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.284 ns ( 72.05 % ) " "Info: Total interconnect delay = 5.284 ns ( 72.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.334 ns" { Clk ShtReg[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.334 ns" { Clk Clk~combout ShtReg[6] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 7.334 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 7.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Clk 1 CLK PIN_127 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 29; CLK Node = 'Clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.284 ns) + CELL(0.918 ns) 7.334 ns SampleCnt\[3\] 2 REG LC_X11_Y6_N3 3 " "Info: 2: + IC(5.284 ns) + CELL(0.918 ns) = 7.334 ns; Loc. = LC_X11_Y6_N3; Fanout = 3; REG Node = 'SampleCnt\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.202 ns" { Clk SampleCnt[3] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.95 % ) " "Info: Total cell delay = 2.050 ns ( 27.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.284 ns ( 72.05 % ) " "Info: Total interconnect delay = 5.284 ns ( 72.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.334 ns" { Clk SampleCnt[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.334 ns" { Clk Clk~combout SampleCnt[3] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.334 ns" { Clk ShtReg[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.334 ns" { Clk Clk~combout ShtReg[6] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.334 ns" { Clk SampleCnt[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.334 ns" { Clk Clk~combout SampleCnt[3] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.238 ns" { SampleCnt[3] Equal1~35 ShtReg[0]~569 ShtReg[0]~570 ShtReg[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.238 ns" { SampleCnt[3] Equal1~35 ShtReg[0]~569 ShtReg[0]~570 ShtReg[6] } { 0.000ns 1.908ns 1.799ns 0.305ns 1.669ns } { 0.000ns 0.914ns 0.200ns 0.200ns 1.243ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.334 ns" { Clk ShtReg[6] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.334 ns" { Clk Clk~combout ShtReg[6] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.334 ns" { Clk SampleCnt[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.334 ns" { Clk Clk~combout SampleCnt[3] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "SampleCnt\[1\] Reset Clk 1.406 ns register " "Info: tsu for register \"SampleCnt\[1\]\" (data pin = \"Reset\", clock pin = \"Clk\") is 1.406 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.407 ns + Longest pin register " "Info: + Longest pin to register delay is 8.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Reset 1 PIN PIN_58 28 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_58; Fanout = 28; PIN Node = 'Reset'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.999 ns) + CELL(0.511 ns) 4.642 ns SampleCnt\[0\]~1181 2 COMB LC_X11_Y6_N0 1 " "Info: 2: + IC(2.999 ns) + CELL(0.511 ns) = 4.642 ns; Loc. = LC_X11_Y6_N0; Fanout = 1; COMB Node = 'SampleCnt\[0\]~1181'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.510 ns" { Reset SampleCnt[0]~1181 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.511 ns) 5.964 ns SampleCnt\[0\]~1183 3 COMB LC_X11_Y6_N6 4 " "Info: 3: + IC(0.811 ns) + CELL(0.511 ns) = 5.964 ns; Loc. = LC_X11_Y6_N6; Fanout = 4; COMB Node = 'SampleCnt\[0\]~1183'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.322 ns" { SampleCnt[0]~1181 SampleCnt[0]~1183 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.852 ns) + CELL(0.591 ns) 8.407 ns SampleCnt\[1\] 4 REG LC_X10_Y5_N4 5 " "Info: 4: + IC(1.852 ns) + CELL(0.591 ns) = 8.407 ns; Loc. = LC_X10_Y5_N4; Fanout = 5; REG Node = 'SampleCnt\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.443 ns" { SampleCnt[0]~1183 SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.745 ns ( 32.65 % ) " "Info: Total cell delay = 2.745 ns ( 32.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.662 ns ( 67.35 % ) " "Info: Total interconnect delay = 5.662 ns ( 67.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.407 ns" { Reset SampleCnt[0]~1181 SampleCnt[0]~1183 SampleCnt[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.407 ns" { Reset Reset~combout SampleCnt[0]~1181 SampleCnt[0]~1183 SampleCnt[1] } { 0.000ns 0.000ns 2.999ns 0.811ns 1.852ns } { 0.000ns 1.132ns 0.511ns 0.511ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 7.334 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk\" to destination register is 7.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Clk 1 CLK PIN_127 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 29; CLK Node = 'Clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.284 ns) + CELL(0.918 ns) 7.334 ns SampleCnt\[1\] 2 REG LC_X10_Y5_N4 5 " "Info: 2: + IC(5.284 ns) + CELL(0.918 ns) = 7.334 ns; Loc. = LC_X10_Y5_N4; Fanout = 5; REG Node = 'SampleCnt\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.202 ns" { Clk SampleCnt[1] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.95 % ) " "Info: Total cell delay = 2.050 ns ( 27.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.284 ns ( 72.05 % ) " "Info: Total interconnect delay = 5.284 ns ( 72.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.334 ns" { Clk SampleCnt[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.334 ns" { Clk Clk~combout SampleCnt[1] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.407 ns" { Reset SampleCnt[0]~1181 SampleCnt[0]~1183 SampleCnt[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.407 ns" { Reset Reset~combout SampleCnt[0]~1181 SampleCnt[0]~1183 SampleCnt[1] } { 0.000ns 0.000ns 2.999ns 0.811ns 1.852ns } { 0.000ns 1.132ns 0.511ns 0.511ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.334 ns" { Clk SampleCnt[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.334 ns" { Clk Clk~combout SampleCnt[1] } { 0.000ns 0.000ns 5.284ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}