{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register SEL:inst2\|Motor_Width_Ctr\[4\] register PWM:inst3\|to_servo 46.28 MHz 21.606 ns Internal " "Info: Clock \"clk\" has Internal fmax of 46.28 MHz between source register \"SEL:inst2\|Motor_Width_Ctr\[4\]\" and destination register \"PWM:inst3\|to_servo\" (period= 21.606 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.281 ns + Longest register register " "Info: + Longest register to register delay is 8.281 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SEL:inst2\|Motor_Width_Ctr\[4\] 1 REG LC_X13_Y9_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y9_N5; Fanout = 2; REG Node = 'SEL:inst2\|Motor_Width_Ctr\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SEL:inst2|Motor_Width_Ctr[4] } "NODE_NAME" } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.859 ns) + CELL(0.954 ns) 2.813 ns PWM:inst3\|Add2~123 2 COMB LC_X14_Y8_N4 3 " "Info: 2: + IC(1.859 ns) + CELL(0.954 ns) = 2.813 ns; Loc. = LC_X14_Y8_N4; Fanout = 3; COMB Node = 'PWM:inst3\|Add2~123'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.813 ns" { SEL:inst2|Motor_Width_Ctr[4] PWM:inst3|Add2~123 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 3.788 ns PWM:inst3\|Add2~118 3 COMB LC_X14_Y8_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.975 ns) = 3.788 ns; Loc. = LC_X14_Y8_N6; Fanout = 2; COMB Node = 'PWM:inst3\|Add2~118'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.975 ns" { PWM:inst3|Add2~123 PWM:inst3|Add2~118 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.978 ns) 5.895 ns PWM:inst3\|LessThan0~451 4 COMB LC_X13_Y8_N6 1 " "Info: 4: + IC(1.129 ns) + CELL(0.978 ns) = 5.895 ns; Loc. = LC_X13_Y8_N6; Fanout = 1; COMB Node = 'PWM:inst3\|LessThan0~451'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.107 ns" { PWM:inst3|Add2~118 PWM:inst3|LessThan0~451 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.815 ns) 6.710 ns PWM:inst3\|LessThan0~443 5 COMB LC_X13_Y8_N7 1 " "Info: 5: + IC(0.000 ns) + CELL(0.815 ns) = 6.710 ns; Loc. = LC_X13_Y8_N7; Fanout = 1; COMB Node = 'PWM:inst3\|LessThan0~443'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.815 ns" { PWM:inst3|LessThan0~451 PWM:inst3|LessThan0~443 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.767 ns) + CELL(0.804 ns) 8.281 ns PWM:inst3\|to_servo 6 REG LC_X13_Y8_N9 1 " "Info: 6: + IC(0.767 ns) + CELL(0.804 ns) = 8.281 ns; Loc. = LC_X13_Y8_N9; Fanout = 1; REG Node = 'PWM:inst3\|to_servo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.571 ns" { PWM:inst3|LessThan0~443 PWM:inst3|to_servo } "NODE_NAME" } } { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/PWM.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.526 ns ( 54.66 % ) " "Info: Total cell delay = 4.526 ns ( 54.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.755 ns ( 45.34 % ) " "Info: Total interconnect delay = 3.755 ns ( 45.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.281 ns" { SEL:inst2|Motor_Width_Ctr[4] PWM:inst3|Add2~123 PWM:inst3|Add2~118 PWM:inst3|LessThan0~451 PWM:inst3|LessThan0~443 PWM:inst3|to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.281 ns" { SEL:inst2|Motor_Width_Ctr[4] PWM:inst3|Add2~123 PWM:inst3|Add2~118 PWM:inst3|LessThan0~451 PWM:inst3|LessThan0~443 PWM:inst3|to_servo } { 0.000ns 1.859ns 0.000ns 1.129ns 0.000ns 0.767ns } { 0.000ns 0.954ns 0.975ns 0.978ns 0.815ns 0.804ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.189 ns - Smallest " "Info: - Smallest clock skew is -2.189 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.615 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.615 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns PWM:inst3\|clk_servo 2 REG LC_X11_Y6_N2 15 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y6_N2; Fanout = 15; REG Node = 'PWM:inst3\|clk_servo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.567 ns" { clk PWM:inst3|clk_servo } "NODE_NAME" } } { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/PWM.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.998 ns) + CELL(0.918 ns) 12.615 ns PWM:inst3\|to_servo 3 REG LC_X13_Y8_N9 1 " "Info: 3: + IC(3.998 ns) + CELL(0.918 ns) = 12.615 ns; Loc. = LC_X13_Y8_N9; Fanout = 1; REG Node = 'PWM:inst3\|to_servo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.916 ns" { PWM:inst3|clk_servo PWM:inst3|to_servo } "NODE_NAME" } } { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/PWM.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 26.51 % ) " "Info: Total cell delay = 3.344 ns ( 26.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.271 ns ( 73.49 % ) " "Info: Total interconnect delay = 9.271 ns ( 73.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.615 ns" { clk PWM:inst3|clk_servo PWM:inst3|to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.615 ns" { clk clk~combout PWM:inst3|clk_servo PWM:inst3|to_servo } { 0.000ns 0.000ns 5.273ns 3.998ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 14.804 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 14.804 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns RxUnit:inst\|DOut\[7\] 2 REG LC_X15_Y6_N2 2 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X15_Y6_N2; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.567 ns" { clk RxUnit:inst|DOut[7] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.665 ns) + CELL(0.511 ns) 10.875 ns SEL:inst2\|comb~0 3 COMB LC_X12_Y3_N2 7 " "Info: 3: + IC(2.665 ns) + CELL(0.511 ns) = 10.875 ns; Loc. = LC_X12_Y3_N2; Fanout = 7; COMB Node = 'SEL:inst2\|comb~0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { RxUnit:inst|DOut[7] SEL:inst2|comb~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.729 ns) + CELL(0.200 ns) 14.804 ns SEL:inst2\|Motor_Width_Ctr\[4\] 4 REG LC_X13_Y9_N5 2 " "Info: 4: + IC(3.729 ns) + CELL(0.200 ns) = 14.804 ns; Loc. = LC_X13_Y9_N5; Fanout = 2; REG Node = 'SEL:inst2\|Motor_Width_Ctr\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.929 ns" { SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[4] } "NODE_NAME" } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.137 ns ( 21.19 % ) " "Info: Total cell delay = 3.137 ns ( 21.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.667 ns ( 78.81 % ) " "Info: Total interconnect delay = 11.667 ns ( 78.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.804 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.804 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[4] } { 0.000ns 0.000ns 5.273ns 2.665ns 3.729ns } { 0.000ns 1.132ns 1.294ns 0.511ns 0.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.615 ns" { clk PWM:inst3|clk_servo PWM:inst3|to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.615 ns" { clk clk~combout PWM:inst3|clk_servo PWM:inst3|to_servo } { 0.000ns 0.000ns 5.273ns 3.998ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.804 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.804 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[4] } { 0.000ns 0.000ns 5.273ns 2.665ns 3.729ns } { 0.000ns 1.132ns 1.294ns 0.511ns 0.200ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/PWM.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/SEL.vhd" 27 -1 0 } } { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/PWM.vhd" 23 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.281 ns" { SEL:inst2|Motor_Width_Ctr[4] PWM:inst3|Add2~123 PWM:inst3|Add2~118 PWM:inst3|LessThan0~451 PWM:inst3|LessThan0~443 PWM:inst3|to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.281 ns" { SEL:inst2|Motor_Width_Ctr[4] PWM:inst3|Add2~123 PWM:inst3|Add2~118 PWM:inst3|LessThan0~451 PWM:inst3|LessThan0~443 PWM:inst3|to_servo } { 0.000ns 1.859ns 0.000ns 1.129ns 0.000ns 0.767ns } { 0.000ns 0.954ns 0.975ns 0.978ns 0.815ns 0.804ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.615 ns" { clk PWM:inst3|clk_servo PWM:inst3|to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.615 ns" { clk clk~combout PWM:inst3|clk_servo PWM:inst3|to_servo } { 0.000ns 0.000ns 5.273ns 3.998ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.804 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.804 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~0 SEL:inst2|Motor_Width_Ctr[4] } { 0.000ns 0.000ns 5.273ns 2.665ns 3.729ns } { 0.000ns 1.132ns 1.294ns 0.511ns 0.200ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 14 " "Warning: Circuit may not operate. Detected 14 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "RxUnit:inst\|DOut\[4\] SEL:inst2\|Servo_Width_Ctr\[4\] clk 5.628 ns " "Info: Found hold time violation between source  pin or register \"RxUnit:inst\|DOut\[4\]\" and destination pin or register \"SEL:inst2\|Servo_Width_Ctr\[4\]\" for clock \"clk\" (Hold time is 5.628 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.639 ns + Largest " "Info: + Largest clock skew is 7.639 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 14.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 14.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns RxUnit:inst\|DOut\[7\] 2 REG LC_X15_Y6_N2 2 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X15_Y6_N2; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[7\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.567 ns" { clk RxUnit:inst|DOut[7] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.665 ns) + CELL(0.511 ns) 10.875 ns SEL:inst2\|comb~1 3 COMB LC_X12_Y3_N4 7 " "Info: 3: + IC(2.665 ns) + CELL(0.511 ns) = 10.875 ns; Loc. = LC_X12_Y3_N4; Fanout = 7; COMB Node = 'SEL:inst2\|comb~1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { RxUnit:inst|DOut[7] SEL:inst2|comb~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.887 ns) + CELL(0.200 ns) 14.962 ns SEL:inst2\|Servo_Width_Ctr\[4\] 4 REG LC_X15_Y6_N0 2 " "Info: 4: + IC(3.887 ns) + CELL(0.200 ns) = 14.962 ns; Loc. = LC_X15_Y6_N0; Fanout = 2; REG Node = 'SEL:inst2\|Servo_Width_Ctr\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.087 ns" { SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[4] } "NODE_NAME" } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.137 ns ( 20.97 % ) " "Info: Total cell delay = 3.137 ns ( 20.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.825 ns ( 79.03 % ) " "Info: Total interconnect delay = 11.825 ns ( 79.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.962 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.962 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[4] } { 0.000ns 0.000ns 5.273ns 2.665ns 3.887ns } { 0.000ns 1.132ns 1.294ns 0.511ns 0.200ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.323 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(0.918 ns) 7.323 ns RxUnit:inst\|DOut\[4\] 2 REG LC_X15_Y6_N9 2 " "Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X15_Y6_N9; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.191 ns" { clk RxUnit:inst|DOut[4] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.99 % ) " "Info: Total cell delay = 2.050 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.273 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.273 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk RxUnit:inst|DOut[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout RxUnit:inst|DOut[4] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.962 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.962 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[4] } { 0.000ns 0.000ns 5.273ns 2.665ns 3.887ns } { 0.000ns 1.132ns 1.294ns 0.511ns 0.200ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk RxUnit:inst|DOut[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout RxUnit:inst|DOut[4] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.635 ns - Shortest register register " "Info: - Shortest register to register delay is 1.635 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RxUnit:inst\|DOut\[4\] 1 REG LC_X15_Y6_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y6_N9; Fanout = 2; REG Node = 'RxUnit:inst\|DOut\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RxUnit:inst|DOut[4] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(0.740 ns) 1.635 ns SEL:inst2\|Servo_Width_Ctr\[4\] 2 REG LC_X15_Y6_N0 2 " "Info: 2: + IC(0.895 ns) + CELL(0.740 ns) = 1.635 ns; Loc. = LC_X15_Y6_N0; Fanout = 2; REG Node = 'SEL:inst2\|Servo_Width_Ctr\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.635 ns" { RxUnit:inst|DOut[4] SEL:inst2|Servo_Width_Ctr[4] } "NODE_NAME" } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.740 ns ( 45.26 % ) " "Info: Total cell delay = 0.740 ns ( 45.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.895 ns ( 54.74 % ) " "Info: Total interconnect delay = 0.895 ns ( 54.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.635 ns" { RxUnit:inst|DOut[4] SEL:inst2|Servo_Width_Ctr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.635 ns" { RxUnit:inst|DOut[4] SEL:inst2|Servo_Width_Ctr[4] } { 0.000ns 0.895ns } { 0.000ns 0.740ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } } { "SEL.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/SEL.vhd" 27 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.962 ns" { clk RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "14.962 ns" { clk clk~combout RxUnit:inst|DOut[7] SEL:inst2|comb~1 SEL:inst2|Servo_Width_Ctr[4] } { 0.000ns 0.000ns 5.273ns 2.665ns 3.887ns } { 0.000ns 1.132ns 1.294ns 0.511ns 0.200ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk RxUnit:inst|DOut[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout RxUnit:inst|DOut[4] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.635 ns" { RxUnit:inst|DOut[4] SEL:inst2|Servo_Width_Ctr[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.635 ns" { RxUnit:inst|DOut[4] SEL:inst2|Servo_Width_Ctr[4] } { 0.000ns 0.895ns } { 0.000ns 0.740ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "RxUnit:inst\|SampleCnt\[2\] rst clk 0.709 ns register " "Info: tsu for register \"RxUnit:inst\|SampleCnt\[2\]\" (data pin = \"rst\", clock pin = \"clk\") is 0.709 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.699 ns + Longest pin register " "Info: + Longest pin to register delay is 7.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_110 57 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_110; Fanout = 57; PIN Node = 'rst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/test.bdf" { { 88 -24 144 104 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.199 ns) + CELL(0.740 ns) 5.071 ns RxUnit:inst\|SampleCnt\[0\]~1174 2 COMB LC_X16_Y6_N0 1 " "Info: 2: + IC(3.199 ns) + CELL(0.740 ns) = 5.071 ns; Loc. = LC_X16_Y6_N0; Fanout = 1; COMB Node = 'RxUnit:inst\|SampleCnt\[0\]~1174'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.939 ns" { rst RxUnit:inst|SampleCnt[0]~1174 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.772 ns) + CELL(0.511 ns) 6.354 ns RxUnit:inst\|SampleCnt\[0\]~1175 3 COMB LC_X16_Y6_N8 4 " "Info: 3: + IC(0.772 ns) + CELL(0.511 ns) = 6.354 ns; Loc. = LC_X16_Y6_N8; Fanout = 4; COMB Node = 'RxUnit:inst\|SampleCnt\[0\]~1175'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.283 ns" { RxUnit:inst|SampleCnt[0]~1174 RxUnit:inst|SampleCnt[0]~1175 } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.754 ns) + CELL(0.591 ns) 7.699 ns RxUnit:inst\|SampleCnt\[2\] 4 REG LC_X16_Y6_N1 4 " "Info: 4: + IC(0.754 ns) + CELL(0.591 ns) = 7.699 ns; Loc. = LC_X16_Y6_N1; Fanout = 4; REG Node = 'RxUnit:inst\|SampleCnt\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.345 ns" { RxUnit:inst|SampleCnt[0]~1175 RxUnit:inst|SampleCnt[2] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.974 ns ( 38.63 % ) " "Info: Total cell delay = 2.974 ns ( 38.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.725 ns ( 61.37 % ) " "Info: Total interconnect delay = 4.725 ns ( 61.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.699 ns" { rst RxUnit:inst|SampleCnt[0]~1174 RxUnit:inst|SampleCnt[0]~1175 RxUnit:inst|SampleCnt[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.699 ns" { rst rst~combout RxUnit:inst|SampleCnt[0]~1174 RxUnit:inst|SampleCnt[0]~1175 RxUnit:inst|SampleCnt[2] } { 0.000ns 0.000ns 3.199ns 0.772ns 0.754ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.323 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(0.918 ns) 7.323 ns RxUnit:inst\|SampleCnt\[2\] 2 REG LC_X16_Y6_N1 4 " "Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X16_Y6_N1; Fanout = 4; REG Node = 'RxUnit:inst\|SampleCnt\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.191 ns" { clk RxUnit:inst|SampleCnt[2] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.99 % ) " "Info: Total cell delay = 2.050 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.273 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.273 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk RxUnit:inst|SampleCnt[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout RxUnit:inst|SampleCnt[2] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.699 ns" { rst RxUnit:inst|SampleCnt[0]~1174 RxUnit:inst|SampleCnt[0]~1175 RxUnit:inst|SampleCnt[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.699 ns" { rst rst~combout RxUnit:inst|SampleCnt[0]~1174 RxUnit:inst|SampleCnt[0]~1175 RxUnit:inst|SampleCnt[2] } { 0.000ns 0.000ns 3.199ns 0.772ns 0.754ns } { 0.000ns 1.132ns 0.740ns 0.511ns 0.591ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk RxUnit:inst|SampleCnt[2] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout RxUnit:inst|SampleCnt[2] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}