{ "Info" "ITDB_FULL_TCO_RESULT" "clk to_motor PWM:inst4\|to_servo 18.611 ns register " "Info: tco from clock \"clk\" to destination pin \"to_motor\" through register \"PWM:inst4\|to_servo\" is 18.611 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.615 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.615 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns PWM:inst3\|clk_servo 2 REG LC_X11_Y6_N2 15 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y6_N2; Fanout = 15; REG Node = 'PWM:inst3\|clk_servo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.567 ns" { clk PWM:inst3|clk_servo } "NODE_NAME" } } { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/PWM.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.998 ns) + CELL(0.918 ns) 12.615 ns PWM:inst4\|to_servo 3 REG LC_X16_Y7_N8 1 " "Info: 3: + IC(3.998 ns) + CELL(0.918 ns) = 12.615 ns; Loc. = LC_X16_Y7_N8; Fanout = 1; REG Node = 'PWM:inst4\|to_servo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.916 ns" { PWM:inst3|clk_servo PWM:inst4|to_servo } "NODE_NAME" } } { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/PWM.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 26.51 % ) " "Info: Total cell delay = 3.344 ns ( 26.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.271 ns ( 73.49 % ) " "Info: Total interconnect delay = 9.271 ns ( 73.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.615 ns" { clk PWM:inst3|clk_servo PWM:inst4|to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.615 ns" { clk clk~combout PWM:inst3|clk_servo PWM:inst4|to_servo } { 0.000ns 0.000ns 5.273ns 3.998ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/PWM.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.620 ns + Longest register pin " "Info: + Longest register to pin delay is 5.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PWM:inst4\|to_servo 1 REG LC_X16_Y7_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y7_N8; Fanout = 1; REG Node = 'PWM:inst4\|to_servo'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PWM:inst4|to_servo } "NODE_NAME" } } { "PWM.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/PWM.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.298 ns) + CELL(2.322 ns) 5.620 ns to_motor 2 PIN PIN_55 0 " "Info: 2: + IC(3.298 ns) + CELL(2.322 ns) = 5.620 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'to_motor'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.620 ns" { PWM:inst4|to_servo to_motor } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/test.bdf" { { 424 552 728 440 "to_motor" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 41.32 % ) " "Info: Total cell delay = 2.322 ns ( 41.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.298 ns ( 58.68 % ) " "Info: Total interconnect delay = 3.298 ns ( 58.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.620 ns" { PWM:inst4|to_servo to_motor } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.620 ns" { PWM:inst4|to_servo to_motor } { 0.000ns 3.298ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.615 ns" { clk PWM:inst3|clk_servo PWM:inst4|to_servo } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.615 ns" { clk clk~combout PWM:inst3|clk_servo PWM:inst4|to_servo } { 0.000ns 0.000ns 5.273ns 3.998ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.620 ns" { PWM:inst4|to_servo to_motor } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.620 ns" { PWM:inst4|to_servo to_motor } { 0.000ns 3.298ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "RxUnit:inst\|ShtReg\[3\] rst clk 2.809 ns register " "Info: th for register \"RxUnit:inst\|ShtReg\[3\]\" (data pin = \"rst\", clock pin = \"clk\") is 2.809 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.323 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.323 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 46 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 46; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/test.bdf" { { 24 -24 144 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(0.918 ns) 7.323 ns RxUnit:inst\|ShtReg\[3\] 2 REG LC_X16_Y8_N6 2 " "Info: 2: + IC(5.273 ns) + CELL(0.918 ns) = 7.323 ns; Loc. = LC_X16_Y8_N6; Fanout = 2; REG Node = 'RxUnit:inst\|ShtReg\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.191 ns" { clk RxUnit:inst|ShtReg[3] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 27.99 % ) " "Info: Total cell delay = 2.050 ns ( 27.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.273 ns ( 72.01 % ) " "Info: Total interconnect delay = 5.273 ns ( 72.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk RxUnit:inst|ShtReg[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout RxUnit:inst|ShtReg[3] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.735 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.735 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_110 57 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_110; Fanout = 57; PIN Node = 'rst'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "test.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/test.bdf" { { 88 -24 144 104 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.542 ns) + CELL(1.061 ns) 4.735 ns RxUnit:inst\|ShtReg\[3\] 2 REG LC_X16_Y8_N6 2 " "Info: 2: + IC(2.542 ns) + CELL(1.061 ns) = 4.735 ns; Loc. = LC_X16_Y8_N6; Fanout = 2; REG Node = 'RxUnit:inst\|ShtReg\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.603 ns" { rst RxUnit:inst|ShtReg[3] } "NODE_NAME" } } { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/小車(chē)速度方向控制/vhdl/RxUnit.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 46.31 % ) " "Info: Total cell delay = 2.193 ns ( 46.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.542 ns ( 53.69 % ) " "Info: Total interconnect delay = 2.542 ns ( 53.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.735 ns" { rst RxUnit:inst|ShtReg[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.735 ns" { rst rst~combout RxUnit:inst|ShtReg[3] } { 0.000ns 0.000ns 2.542ns } { 0.000ns 1.132ns 1.061ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.323 ns" { clk RxUnit:inst|ShtReg[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "7.323 ns" { clk clk~combout RxUnit:inst|ShtReg[3] } { 0.000ns 0.000ns 5.273ns } { 0.000ns 1.132ns 0.918ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.735 ns" { rst RxUnit:inst|ShtReg[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.735 ns" { rst rst~combout RxUnit:inst|ShtReg[3] } { 0.000ns 0.000ns 2.542ns } { 0.000ns 1.132ns 1.061ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 18 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 21 20:01:21 2007 " "Info: Processing ended: Fri Sep 21 20:01:21 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}