Information: Updating design information... (UID-85) ****************************************Report : areaDesign : PhoneVersion: 2001.08Date   : Sun Dec 24 00:02:29 2006****************************************Library(s) Used:    lsi_10k (File: /net/eda450/disk1/synopsys/Synthesis01.08/libraries/syn/lsi_10k.db)Number of ports:                7Number of nets:                38Number of cells:               25Number of references:          13Combinational area:         33.000000Noncombinational area:      78.000000Net Interconnect area:      undefined  (No wire load specified)Total cell area:           111.000000Total area:                 undefined1design_analyzer> Information: Updating design information... (UID-85)Performing power analysis through design. (low effort)Warning: There is no defined clock in the design. (PWR-80)Warning: There are sequential cells with no output activity annotation. (PWR-96)Warning: Sequential cell rc_reg with no output activity annotation. (PWR-81)Warning: Sequential cell brc_reg with no output activity annotation. (PWR-81)Warning: Sequential cell bcc_reg with no output activity annotation. (PWR-81)Warning: Sequential cell State_reg[2] with no output activity annotation. (PWR-81)Warning: Sequential cell State_reg[0] with no output activity annotation. (PWR-81)Warning: Sequential cell State_reg[1] with no output activity annotation. (PWR-81) ****************************************Report : power	-analysis_effort lowDesign : PhoneVersion: 2001.08Date   : Sun Dec 24 00:02:34 2006****************************************Library(s) Used:    lsi_10k (File: /net/eda450/disk1/synopsys/Synthesis01.08/libraries/syn/lsi_10k.db)Warning: The library cells used by your design are not characterized for internal power. (PWR-26)Operating Conditions: Wire Load Model Mode: topGlobal Operating Voltage = 5    Power-specific unit information :    Voltage Units = 1V    Capacitance Units = 0.100000ff    Time Units = 1ns    Dynamic Power Units = 100nW    (derived from V,C,T units)    Leakage Power Units = Unitless  Cell Internal Power  =   0.0000 nW    (0%)  Net Switching Power  =  28.3285 uW  (100%)                         ---------Total Dynamic Power    =  28.3285 uW  (100%)Cell Leakage Power     =   0.0000 1design_analyzer>  ****************************************Report : timing        -path full        -delay max        -max_paths 1Design : PhoneVersion: 2001.08Date   : Sun Dec 24 00:02:34 2006****************************************Operating Conditions: Wire Load Model Mode: top  Startpoint: bcc_reg (rising edge-triggered flip-flop)  Endpoint: bcc (output port)  Path Group: (none)  Path Type: max  Point                                    Incr       Path  -----------------------------------------------------------  bcc_reg/CP (FJK2S)                       0.00       0.00 r  bcc_reg/Q (FJK2S)                        1.47       1.47 r  bcc (out)                                0.00       1.47 r  data arrival time                                   1.47  -----------------------------------------------------------  (Path is unconstrained)1design_analyzer>