?? flashloader.acf

?? intel flash控制器VHDL 源代碼
?? ACF
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	DEFAULT_9K_EXP_PER_LCELL = 1/2;
	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
	LCELLS_PER_ROW_PERCENT = 100;
	FAN_IN_PER_LCELL_PERCENT = 100;
	EXP_PER_LCELL_PERCENT = 100;
	ROW_PINS_PERCENT = 50;
	ORIGINAL_MAXPLUS2_VERSION = 10.0;
	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
	PARALLEL_EXPANDERS = OFF;
	REGISTER_OPTIMIZATION = ON;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
	CARRY_CHAIN_LENGTH = 32;
	CASCADE_CHAIN_LENGTH = 2;
	REGISTER_OPTIMIZATION = ON;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	IGNORE_SOFT_BUFFERS = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
	PARALLEL_EXPANDERS = ON;
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = AUTO;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = AUTO;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = MANUAL;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = MANUAL;
END;
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?? 文件大小 20 K
?? 上傳用戶 GreatMarxist
?? 所屬分類 VHDL/FPGA/Verilog
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#intel #flash #VHDL #控制器
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