library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;

entity pcif is
	port (	DATA_MODE  : in std_logic ;
		DATA_PC	   : in std_logic ;
		STB	   : in std_logic ;
		CLK33	   : in std_logic ;
		RSTB	   : in std_logic ;
		INIT_ST	   : in std_logic ;
		VERI_ST    : in std_logic ;
		VERI_ACK   : in std_logic ;
 		EN_FLASH   : out std_logic ;
		EN_APEX	   : out std_logic ;
		EN_LAST	   : out std_logic ;
		EN_VERIFY  : out std_logic ;
  		DATA_OUT   : out std_logic_vector(7 downto 0) ;
		INIT_EN	   : out std_logic ;
		MODE_U	   : out std_logic ;
		STB_UP     : out std_logic ;
		CNT3V_C    : out std_logic ;
		COUNT      : out std_logic_vector(2 downto 0) ;
		ACK	   : out std_logic
		);
end pcif;

architecture rtl of pcif is

signal MODE_1S	     : std_logic ;
signal MODE_2S	     : std_logic ;
signal PC_DA	     : std_logic ;
signal STB_1S	     : std_logic ;
signal STB_2S	     : std_logic ;
signal INIT_ST_1S    : std_logic ;
signal STB_U	     : std_logic ;
signal STB_D	     : std_logic ;
signal MODE_D	     : std_logic ;
signal INIT_U	     : std_logic ;
signal INIT_D	     : std_logic ;
signal ENB_FL	     : std_logic ;
signal ENABLE	     : std_logic ;
signal ACK_ENB	     : std_logic ;
signal ACK_MSK	     : std_logic ;
signal DA_EN_A	     : std_logic ;
signal DA_EN_B	     : std_logic ;
signal CNT_A         : std_logic_vector(2 downto 0);
signal CNTA_4	     : std_logic ;
signal CNT_B         : std_logic_vector(2 downto 0);
signal CNTB_4        : std_logic ;
signal REG_A         : std_logic_vector(3 downto 0);
signal REG_B         : std_logic_vector(3 downto 0);
signal REG           : std_logic_vector(7 downto 0);
signal CMD_EN_A      : std_logic ;
signal CMD_EN_B      : std_logic ;
signal CMD_M         : std_logic_vector (1 downto 0);
signal EN_FLASH_TEMP : std_logic ;
signal EN_VERIFY_TEMP: std_logic ;
signal CNT3V	     : std_logic_vector(2 downto 0);
signal CNT3V_7       : std_logic ;


begin
-- PC I/F -----------------------------------------------------------

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			MODE_1S <= '0' ;
			MODE_2S <= '0' ;
		elsif (CLK33'event and CLK33='1') then
			MODE_1S <= DATA_MODE ;
			MODE_2S <= MODE_1S ;
		end if ;
	end process ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			PC_DA <= '0' ;
		elsif (CLK33'event and CLK33='1') then
			PC_DA <= DATA_PC ;
		end if ;
	end process ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			STB_1S <= '0' ;
			STB_2S <= '0' ;
		elsif (CLK33'event and CLK33='1') then
			STB_1S <= STB ;
			STB_2S <= STB_1S ;
		end if ;
	end process ;

-- INIT_ST bicun pulse ----------------------------------------------

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			INIT_ST_1S <= '0' ;
		elsif (CLK33'event and CLK33='1') then
			INIT_ST_1S <= INIT_ST ;
		end if ;
	end process ;

-- bibun pulse ------------------------------------------------------

	STB_U <= STB_1S and not(STB_2S) ;
	STB_D <= not(STB_1S) and STB_2S ;
        STB_UP <= STB_U ;


	MODE_U <= MODE_1S and not(MODE_2S) ;
	MODE_D <= not(MODE_1S) and MODE_2S ;

	INIT_U <= INIT_ST and not(INIT_ST_1S) ;
	INIT_D <= not(INIT_ST) and INIT_ST_1S ;

-- enable create ----------------------------------------------------

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			ENABLE <= '0' ;
		elsif (CLK33'event and CLK33='1') then
			if (MODE_D='1') then
				ENABLE <= '1' ;
			elsif (INIT_D='1') then
				ENABLE <= '0' ;
			end if ;
		end if ;
	end process ;

	ENB_FL <= INIT_ST_1S and CNTB_4 ;
	INIT_EN <= ENB_FL when (EN_FLASH_TEMP='1') else ENABLE ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			ACK_ENB <= '1' ;
		elsif (CLK33'event and CLK33='1') then
			if (MODE_D='1' and EN_VERIFY_TEMP='0') then
				ACK_ENB <= '1' ;
			elsif (INIT_U='1') then
				ACK_ENB <= '0' ;
			end if ;
		end if ;
	end process ;

	ACK_MSK <= CNTA_4 when (EN_FLASH_TEMP='1') else ((ACK_ENB) or (VERI_ACK));
	ACK <= '1' when (ACK_MSK='1') else STB_1S ;

-- serial -> parallel(8bit) -----------------------------------------

	DA_EN_A <= INIT_ST and EN_FLASH_TEMP and not(MODE_1S) and STB_U ;
	DA_EN_B <= INIT_ST and EN_FLASH_TEMP and not(MODE_1S) and STB_D ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			CNT_A <= "000" ;
		elsif (CLK33'event and CLK33='1') then
			if (INIT_U='1') then
				CNT_A <= "000" ;
			elsif (DA_EN_A='1') then
				CNT_A <= CNT_A + 1 ;
			end if ;
		end if ;
	end process ;

	CNTA_4 <= '1' when (CNT_A="100") else '0' ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			CNT_B <= "000" ;
		elsif (CLK33'event and CLK33='1') then
			if (INIT_U='1') then
				CNT_B <= "000" ;
			elsif (DA_EN_B='1') then
				CNT_B <= CNT_B + 1 ;
			end if ;
		end if ;
	end process ;

	CNTB_4 <= '1' when (CNT_B="100") else '0' ;

	process (CLK33, RSTB) begin
 		if (RSTB='0') then
			REG_A <= "0000" ;
		elsif (CLK33'event and CLK33='1') then
			if (INIT_U='1') then
				REG_A <= "0000" ;
			elsif (DA_EN_A = '1') then
				REG_A(0) <= PC_DA ;
				REG_A(1) <= REG_A(0) ;
				REG_A(2) <= REG_A(1) ;
     				REG_A(3) <= REG_A(2) ;
			end if ;
		end if ;
	end process ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			REG_B <= "0000" ;
		elsif (CLK33'event and CLK33='1') then
			if (INIT_U='1') then
				REG_B <= "0000" ;
			elsif (DA_EN_B='1') then
				REG_B(0) <= PC_DA ;
				REG_B(1) <= REG_B(0) ;
				REG_B(2) <= REG_B(1) ;
     				REG_B(3) <= REG_B(2) ;
			end if ;
		end if ;
	end process ;

	process (CNTB_4, REG_A, REG_B) begin
		if (CNTB_4='1') then
  			REG(7) <= REG_B(0) ;
  			REG(6) <= REG_A(0) ;
  			REG(5) <= REG_B(1) ;
  			REG(4) <= REG_A(1) ;
  			REG(3) <= REG_B(2) ;
  			REG(2) <= REG_A(2) ;
  			REG(1) <= REG_B(3) ;
  			REG(0) <= REG_A(3) ;
		else
	  		REG(7) <= '0' ;
  			REG(6) <= '0' ;
  			REG(5) <= '0' ;
  			REG(4) <= '0' ;
  			REG(3) <= '0' ;
  			REG(2) <= '0' ;
  			REG(1) <= '0' ;
  			REG(0) <= '0' ;
		end if;
	end process;

	DATA_OUT <= REG;

-- comand set -------------------------------------------------------

	CMD_EN_A <= MODE_1S and STB_U ;
	CMD_EN_B <= MODE_1S and STB_D ;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			CMD_M(0) <= '1' ;
		elsif (CLK33'event and CLK33='1') then
			if (CMD_EN_A='1') then
				CMD_M(0) <= PC_DA ;
  	 	 	end if;
		end if;
	end process;

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			CMD_M(1) <= '0' ;
		elsif (CLK33'event and CLK33='1') then
			if (CMD_EN_B='1') then
				CMD_M(1) <= PC_DA ;
		  	  end if;
     		end if;
	end process;

	process (CMD_M) begin
		case CMD_M is
   			when "00" =>
				EN_LAST	        <='1';
	  			EN_FLASH_TEMP   <='0';
	  			EN_APEX         <='0';
				EN_VERIFY_TEMP  <='0';
			when "01" =>
				EN_LAST	        <='0';
	  			EN_FLASH_TEMP   <='0';
	  			EN_APEX         <='1';
				EN_VERIFY_TEMP  <='0';
			when "10" =>
				EN_LAST	        <='0';
	  			EN_FLASH_TEMP   <='1';
	  			EN_APEX         <='0';
				EN_VERIFY_TEMP  <='0';
			when "11" =>
				EN_LAST	        <='0';
	  			EN_FLASH_TEMP   <='0';
	  			EN_APEX         <='0';
				EN_VERIFY_TEMP  <='1';
			when others =>
				EN_LAST	        <='0';
	  			EN_FLASH_TEMP   <='0';
	  			EN_APEX         <='0';
				EN_VERIFY_TEMP  <='0';
	  	end case;
	end process;

	EN_FLASH <= EN_FLASH_TEMP ;
	EN_VERIFY <= EN_VERIFY_TEMP ;

-- 3bit Counter -----------------------------------------------------

	process (CLK33, RSTB) begin
		if (RSTB='0') then
			CNT3V <= "000" ;
		elsif (CLK33'event and CLK33='1') then
			if (VERI_ST='1' and STB_D='1') then
				CNT3V <= CNT3V + '1' ;
			end if;
     		end if;
	end process;

	COUNT <= CNT3V ;
	CNT3V_7 <= '1' when CNT3V="111" else '0' ;
	CNT3V_C <= CNT3V_7 and STB_D ;

---------------------------------------------------------------------
end rtl;