?? led.vhd
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--**********************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
--*********************************************************
ENTITY LED IS --?????
port( clk: in std_logic;
n1,n2,n3,n4,n5,n6:in std_logic_vector(3 downto 0);
wei:out std_logic_vector(5 downto 0);
dan: out std_logic_vector(6 downto 0));
END LED;
--*********************************************************
ARCHITECTURE zx OF LED IS
signal clk1:std_logic;
--******************************************************************
function coding (num:std_logic_vector(3 downto 0)) return std_logic_vector is
variable tmwei:std_logic_vector(6 downto 0);
begin
case num is
when "0000"=>tmwei:="1111110";
when "0001"=>tmwei:="0110000";
when "0010"=>tmwei:="1101101";
when "0011"=>tmwei:="1111001";
when "0100"=>tmwei:="0110011";
when "0101"=>tmwei:="1011011";
when "0110"=>tmwei:="1011111";
when "0111"=>tmwei:="1110000";
when "1000"=>tmwei:="1111111";
when "1001"=>tmwei:="1111011";
when others=>tmwei:="0000000";
end case ;
return tmwei;
end coding;
--************************************************************
begin
process(clk)
variable com:integer range 0 to 10000;
begin
if( clk 'event and clk='1') then
if(com=10000) then com:=0;clk1<=not clk1;
else com:=com+1;
end if;
end if;
end process;
--*****************??????*****************************************
process(clk1)
variable x: integer range 0 to 5;
begin
if(clk1'event and clk1='1') then
if(x=5) then x:=0;
else x:=x+1;
end if;
case x is
when 0=>wei<="000001";dan<=coding(n1);
when 1=>wei<="000010";dan<=coding(n2);
when 2=>wei<="000100";dan<=coding(n3);
when 3=>wei<="001000";dan<=coding(n4);
when 4=>wei<="010000";dan<=coding(n5);
when 5=>wei<="100000";dan<=coding(n6);
when others=>wei<="000000";
end case;
end if;
end process;
END zx;
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