{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.110 ns register register " "Info: Estimated most critical path is register to register delay of 8.110 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns testfreq:inst3\|count3\[0\] 1 REG LAB_X15_Y5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y5; Fanout = 3; REG Node = 'testfreq:inst3\|count3\[0\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { testfreq:inst3|count3[0] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/復件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.160 ns) + CELL(0.575 ns) 1.735 ns testfreq:inst3\|Add2~300COUT1 2 COMB LAB_X15_Y4 2 " "Info: 2: + IC(1.160 ns) + CELL(0.575 ns) = 1.735 ns; Loc. = LAB_X15_Y4; Fanout = 2; COMB Node = 'testfreq:inst3\|Add2~300COUT1'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.735 ns" { testfreq:inst3|count3[0] testfreq:inst3|Add2~300COUT1 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/復件 testfreq/testfreq.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.815 ns testfreq:inst3\|Add2~298COUT1 3 COMB LAB_X15_Y4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.815 ns; Loc. = LAB_X15_Y4; Fanout = 2; COMB Node = 'testfreq:inst3\|Add2~298COUT1'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { testfreq:inst3|Add2~300COUT1 testfreq:inst3|Add2~298COUT1 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/復件 testfreq/testfreq.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.423 ns testfreq:inst3\|Add2~301 4 COMB LAB_X15_Y4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.608 ns) = 2.423 ns; Loc. = LAB_X15_Y4; Fanout = 2; COMB Node = 'testfreq:inst3\|Add2~301'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { testfreq:inst3|Add2~298COUT1 testfreq:inst3|Add2~301 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/復件 testfreq/testfreq.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.061 ns) + CELL(0.292 ns) 3.776 ns testfreq:inst3\|count2\[19\]~951 5 COMB LAB_X15_Y5 1 " "Info: 5: + IC(1.061 ns) + CELL(0.292 ns) = 3.776 ns; Loc. = LAB_X15_Y5; Fanout = 1; COMB Node = 'testfreq:inst3\|count2\[19\]~951'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.353 ns" { testfreq:inst3|Add2~301 testfreq:inst3|count2[19]~951 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/復件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.590 ns) 5.129 ns testfreq:inst3\|count2\[19\]~955 6 COMB LAB_X16_Y4 1 " "Info: 6: + IC(0.763 ns) + CELL(0.590 ns) = 5.129 ns; Loc. = LAB_X16_Y4; Fanout = 1; COMB Node = 'testfreq:inst3\|count2\[19\]~955'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.353 ns" { testfreq:inst3|count2[19]~951 testfreq:inst3|count2[19]~955 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/復件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.064 ns) + CELL(0.590 ns) 5.783 ns testfreq:inst3\|count2\[19\]~957 7 COMB LAB_X16_Y4 20 " "Info: 7: + IC(0.064 ns) + CELL(0.590 ns) = 5.783 ns; Loc. = LAB_X16_Y4; Fanout = 20; COMB Node = 'testfreq:inst3\|count2\[19\]~957'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { testfreq:inst3|count2[19]~955 testfreq:inst3|count2[19]~957 } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/復件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.460 ns) + CELL(0.867 ns) 8.110 ns testfreq:inst3\|count2\[19\] 8 REG LAB_X20_Y3 2 " "Info: 8: + IC(1.460 ns) + CELL(0.867 ns) = 8.110 ns; Loc. = LAB_X20_Y3; Fanout = 2; REG Node = 'testfreq:inst3\|count2\[19\]'" {  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.327 ns" { testfreq:inst3|count2[19]~957 testfreq:inst3|count2[19] } "NODE_NAME" } } { "testfreq.vhd" "" { Text "D:/Project/Quartus II/復件 testfreq/testfreq.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.602 ns ( 44.41 % ) " "Info: Total cell delay = 3.602 ns ( 44.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.508 ns ( 55.59 % ) " "Info: Total interconnect delay = 4.508 ns ( 55.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.110 ns" { testfreq:inst3|count3[0] testfreq:inst3|Add2~300COUT1 testfreq:inst3|Add2~298COUT1 testfreq:inst3|Add2~301 testfreq:inst3|count2[19]~951 testfreq:inst3|count2[19]~955 testfreq:inst3|count2[19]~957 testfreq:inst3|count2[19] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 3 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 3%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X27_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 23 10:01:19 2007 " "Info: Processing ended: Thu Aug 23 10:01:19 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Project/Quartus II/復件 testfreq/testfreq.fit.smsg " "Info: Generated suppressed messages file D:/Project/Quartus II/復件 testfreq/testfreq.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}