|Block1
dan[0] <= LED:inst1.dan[0]
dan[1] <= LED:inst1.dan[1]
dan[2] <= LED:inst1.dan[2]
dan[3] <= LED:inst1.dan[3]
dan[4] <= LED:inst1.dan[4]
dan[5] <= LED:inst1.dan[5]
dan[6] <= LED:inst1.dan[6]
clk => LED:inst1.clk
clk => Dec_to_BCD:inst.clk
clk => testfreq:inst3.clk
clock => testfreq:inst3.clock
wie[0] <= LED:inst1.wei[0]
wie[1] <= LED:inst1.wei[1]
wie[2] <= LED:inst1.wei[2]
wie[3] <= LED:inst1.wei[3]
wie[4] <= LED:inst1.wei[4]
wie[5] <= LED:inst1.wei[5]


|Block1|LED:inst1
clk => clk1.CLK
clk => com[0].CLK
clk => com[1].CLK
clk => com[2].CLK
clk => com[3].CLK
clk => com[4].CLK
clk => com[5].CLK
clk => com[6].CLK
clk => com[7].CLK
clk => com[8].CLK
clk => com[9].CLK
clk => com[10].CLK
clk => com[11].CLK
clk => com[12].CLK
clk => com[13].CLK
n1[0] => Mux0.IN19
n1[0] => Mux1.IN19
n1[0] => Mux2.IN19
n1[0] => Mux3.IN19
n1[0] => Mux4.IN19
n1[0] => Mux5.IN19
n1[0] => Mux6.IN19
n1[1] => Mux0.IN18
n1[1] => Mux1.IN18
n1[1] => Mux2.IN18
n1[1] => Mux3.IN18
n1[1] => Mux4.IN18
n1[1] => Mux5.IN18
n1[1] => Mux6.IN18
n1[2] => Mux0.IN17
n1[2] => Mux1.IN17
n1[2] => Mux2.IN17
n1[2] => Mux3.IN17
n1[2] => Mux4.IN17
n1[2] => Mux5.IN17
n1[2] => Mux6.IN17
n1[3] => Mux0.IN16
n1[3] => Mux1.IN16
n1[3] => Mux2.IN16
n1[3] => Mux3.IN16
n1[3] => Mux4.IN16
n1[3] => Mux5.IN16
n1[3] => Mux6.IN16
n2[0] => Mux7.IN19
n2[0] => Mux8.IN19
n2[0] => Mux9.IN19
n2[0] => Mux10.IN19
n2[0] => Mux11.IN19
n2[0] => Mux12.IN19
n2[0] => Mux13.IN19
n2[1] => Mux7.IN18
n2[1] => Mux8.IN18
n2[1] => Mux9.IN18
n2[1] => Mux10.IN18
n2[1] => Mux11.IN18
n2[1] => Mux12.IN18
n2[1] => Mux13.IN18
n2[2] => Mux7.IN17
n2[2] => Mux8.IN17
n2[2] => Mux9.IN17
n2[2] => Mux10.IN17
n2[2] => Mux11.IN17
n2[2] => Mux12.IN17
n2[2] => Mux13.IN17
n2[3] => Mux7.IN16
n2[3] => Mux8.IN16
n2[3] => Mux9.IN16
n2[3] => Mux10.IN16
n2[3] => Mux11.IN16
n2[3] => Mux12.IN16
n2[3] => Mux13.IN16
n3[0] => Mux14.IN19
n3[0] => Mux15.IN19
n3[0] => Mux16.IN19
n3[0] => Mux17.IN19
n3[0] => Mux18.IN19
n3[0] => Mux19.IN19
n3[0] => Mux20.IN19
n3[1] => Mux14.IN18
n3[1] => Mux15.IN18
n3[1] => Mux16.IN18
n3[1] => Mux17.IN18
n3[1] => Mux18.IN18
n3[1] => Mux19.IN18
n3[1] => Mux20.IN18
n3[2] => Mux14.IN17
n3[2] => Mux15.IN17
n3[2] => Mux16.IN17
n3[2] => Mux17.IN17
n3[2] => Mux18.IN17
n3[2] => Mux19.IN17
n3[2] => Mux20.IN17
n3[3] => Mux14.IN16
n3[3] => Mux15.IN16
n3[3] => Mux16.IN16
n3[3] => Mux17.IN16
n3[3] => Mux18.IN16
n3[3] => Mux19.IN16
n3[3] => Mux20.IN16
n4[0] => Mux21.IN19
n4[0] => Mux22.IN19
n4[0] => Mux23.IN19
n4[0] => Mux24.IN19
n4[0] => Mux25.IN19
n4[0] => Mux26.IN19
n4[0] => Mux27.IN19
n4[1] => Mux21.IN18
n4[1] => Mux22.IN18
n4[1] => Mux23.IN18
n4[1] => Mux24.IN18
n4[1] => Mux25.IN18
n4[1] => Mux26.IN18
n4[1] => Mux27.IN18
n4[2] => Mux21.IN17
n4[2] => Mux22.IN17
n4[2] => Mux23.IN17
n4[2] => Mux24.IN17
n4[2] => Mux25.IN17
n4[2] => Mux26.IN17
n4[2] => Mux27.IN17
n4[3] => Mux21.IN16
n4[3] => Mux22.IN16
n4[3] => Mux23.IN16
n4[3] => Mux24.IN16
n4[3] => Mux25.IN16
n4[3] => Mux26.IN16
n4[3] => Mux27.IN16
n5[0] => Mux28.IN19
n5[0] => Mux29.IN19
n5[0] => Mux30.IN19
n5[0] => Mux31.IN19
n5[0] => Mux32.IN19
n5[0] => Mux33.IN19
n5[0] => Mux34.IN19
n5[1] => Mux28.IN18
n5[1] => Mux29.IN18
n5[1] => Mux30.IN18
n5[1] => Mux31.IN18
n5[1] => Mux32.IN18
n5[1] => Mux33.IN18
n5[1] => Mux34.IN18
n5[2] => Mux28.IN17
n5[2] => Mux29.IN17
n5[2] => Mux30.IN17
n5[2] => Mux31.IN17
n5[2] => Mux32.IN17
n5[2] => Mux33.IN17
n5[2] => Mux34.IN17
n5[3] => Mux28.IN16
n5[3] => Mux29.IN16
n5[3] => Mux30.IN16
n5[3] => Mux31.IN16
n5[3] => Mux32.IN16
n5[3] => Mux33.IN16
n5[3] => Mux34.IN16
n6[0] => Mux35.IN19
n6[0] => Mux36.IN19
n6[0] => Mux37.IN19
n6[0] => Mux38.IN19
n6[0] => Mux39.IN19
n6[0] => Mux40.IN19
n6[0] => Mux41.IN19
n6[1] => Mux35.IN18
n6[1] => Mux36.IN18
n6[1] => Mux37.IN18
n6[1] => Mux38.IN18
n6[1] => Mux39.IN18
n6[1] => Mux40.IN18
n6[1] => Mux41.IN18
n6[2] => Mux35.IN17
n6[2] => Mux36.IN17
n6[2] => Mux37.IN17
n6[2] => Mux38.IN17
n6[2] => Mux39.IN17
n6[2] => Mux40.IN17
n6[2] => Mux41.IN17
n6[3] => Mux35.IN16
n6[3] => Mux36.IN16
n6[3] => Mux37.IN16
n6[3] => Mux38.IN16
n6[3] => Mux39.IN16
n6[3] => Mux40.IN16
n6[3] => Mux41.IN16
wei[0] <= wei[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wei[1] <= wei[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wei[2] <= wei[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wei[3] <= wei[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wei[4] <= wei[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wei[5] <= wei[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dan[0] <= dan[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dan[1] <= dan[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dan[2] <= dan[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dan[3] <= dan[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dan[4] <= dan[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dan[5] <= dan[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dan[6] <= dan[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Block1|Dec_to_BCD:inst
clk => n6[0]~reg0.CLK
clk => n6[1]~reg0.CLK
clk => n6[2]~reg0.CLK
clk => n6[3]~reg0.CLK
clk => n5[0]~reg0.CLK
clk => n5[1]~reg0.CLK
clk => n5[2]~reg0.CLK
clk => n5[3]~reg0.CLK
clk => n4[0]~reg0.CLK
clk => n4[1]~reg0.CLK
clk => n4[2]~reg0.CLK
clk => n4[3]~reg0.CLK
clk => n3[0]~reg0.CLK
clk => n3[1]~reg0.CLK
clk => n3[2]~reg0.CLK
clk => n3[3]~reg0.CLK
clk => n2[0]~reg0.CLK
clk => n2[1]~reg0.CLK
clk => n2[2]~reg0.CLK
clk => n2[3]~reg0.CLK
clk => n1[0]~reg0.CLK
clk => n1[1]~reg0.CLK
clk => n1[2]~reg0.CLK
clk => n1[3]~reg0.CLK
clk => com[0].CLK
clk => com[1].CLK
clk => com[2].CLK
clk => com[3].CLK
clk => com[4].CLK
clk => com[5].CLK
clk => com[6].CLK
clk => com[7].CLK
clk => com[8].CLK
clk => com[9].CLK
clk => com[10].CLK
clk => com[11].CLK
clk => com[12].CLK
clk => com[13].CLK
clk => com[14].CLK
clk => com[15].CLK
clk => com[16].CLK
clk => com[17].CLK
clk => com[18].CLK
clk => com[19].CLK
clk => n66[0].CLK
clk => n66[1].CLK
clk => n66[2].CLK
clk => n66[3].CLK
clk => n55[0].CLK
clk => n55[1].CLK
clk => n55[2].CLK
clk => n55[3].CLK
clk => n44[0].CLK
clk => n44[1].CLK
clk => n44[2].CLK
clk => n44[3].CLK
clk => n33[0].CLK
clk => n33[1].CLK
clk => n33[2].CLK
clk => n33[3].CLK
clk => n22[0].CLK
clk => n22[1].CLK
clk => n22[2].CLK
clk => n22[3].CLK
clk => n11[0].CLK
clk => n11[1].CLK
clk => n11[2].CLK
clk => n11[3].CLK
num[0] => LessThan0.IN20
num[1] => LessThan0.IN19
num[2] => LessThan0.IN18
num[3] => LessThan0.IN17
num[4] => LessThan0.IN16
num[5] => LessThan0.IN15
num[6] => LessThan0.IN14
num[7] => LessThan0.IN13
num[8] => LessThan0.IN12
num[9] => LessThan0.IN11
num[10] => LessThan0.IN10
num[11] => LessThan0.IN9
num[12] => LessThan0.IN8
num[13] => LessThan0.IN7
num[14] => LessThan0.IN6
num[15] => LessThan0.IN5
num[16] => LessThan0.IN4
num[17] => LessThan0.IN3
num[18] => LessThan0.IN2
num[19] => LessThan0.IN1
n1[0] <= n1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n1[1] <= n1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n1[2] <= n1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n1[3] <= n1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n2[0] <= n2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n2[1] <= n2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n2[2] <= n2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n2[3] <= n2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n3[0] <= n3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n3[1] <= n3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n3[2] <= n3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n3[3] <= n3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n4[0] <= n4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n4[1] <= n4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n4[2] <= n4[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n4[3] <= n4[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n5[0] <= n5[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n5[1] <= n5[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n5[2] <= n5[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n5[3] <= n5[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n6[0] <= n6[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n6[1] <= n6[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n6[2] <= n6[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
n6[3] <= n6[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|Block1|testfreq:inst3
clk => freq[0]~reg0.CLK
clk => freq[1]~reg0.CLK
clk => freq[2]~reg0.CLK
clk => freq[3]~reg0.CLK
clk => freq[4]~reg0.CLK
clk => freq[5]~reg0.CLK
clk => freq[6]~reg0.CLK
clk => freq[7]~reg0.CLK
clk => freq[8]~reg0.CLK
clk => freq[9]~reg0.CLK
clk => freq[10]~reg0.CLK
clk => freq[11]~reg0.CLK
clk => freq[12]~reg0.CLK
clk => freq[13]~reg0.CLK
clk => freq[14]~reg0.CLK
clk => freq[15]~reg0.CLK
clk => freq[16]~reg0.CLK
clk => freq[17]~reg0.CLK
clk => freq[18]~reg0.CLK
clk => freq[19]~reg0.CLK
clk => clk1.CLK
clk => count1[0].CLK
clk => count1[1].CLK
clk => count1[2].CLK
clk => count1[3].CLK
clk => count1[4].CLK
clk => count1[5].CLK
clk => count1[6].CLK
clk => count1[7].CLK
clk => count1[8].CLK
clk => count1[9].CLK
clk => count1[10].CLK
clk => count1[11].CLK
clk => count1[12].CLK
clk => count1[13].CLK
clk => count1[14].CLK
clk => count1[15].CLK
clk => count1[16].CLK
clk => count1[17].CLK
clk => count1[18].CLK
clk => count1[19].CLK
clk => count1[20].CLK
clk => count1[21].CLK
clk => count1[22].CLK
clk => count1[23].CLK
clk => count1[24].CLK
clk => count1[25].CLK
clk => clr.CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => count[5].CLK
clk => count[6].CLK
clk => count[7].CLK
clk => count[8].CLK
clk => count[9].CLK
clk => count[10].CLK
clk => count[11].CLK
clk => count[12].CLK
clk => count[13].CLK
clk => count[14].CLK
clk => count[15].CLK
clk => count[16].CLK
clk => count[17].CLK
clk => count[18].CLK
clk => count[19].CLK
clk => count[20].CLK
clk => count[21].CLK
clk => count[22].CLK
clk => count[23].CLK
clk => count[24].CLK
clk => count[25].CLK
clock => count2[0].CLK
clock => count2[1].CLK
clock => count2[2].CLK
clock => count2[3].CLK
clock => count2[4].CLK
clock => count2[5].CLK
clock => count2[6].CLK
clock => count2[7].CLK
clock => count2[8].CLK
clock => count2[9].CLK
clock => count2[10].CLK
clock => count2[11].CLK
clock => count2[12].CLK
clock => count2[13].CLK
clock => count2[14].CLK
clock => count2[15].CLK
clock => count2[16].CLK
clock => count2[17].CLK
clock => count2[18].CLK
clock => count2[19].CLK
freq[0] <= freq[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[1] <= freq[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[2] <= freq[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[3] <= freq[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[4] <= freq[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[5] <= freq[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[6] <= freq[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[7] <= freq[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[8] <= freq[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[9] <= freq[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[10] <= freq[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[11] <= freq[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[12] <= freq[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[13] <= freq[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[14] <= freq[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[15] <= freq[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[16] <= freq[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[17] <= freq[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[18] <= freq[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
freq[19] <= freq[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE