module threediv_clk(rst,clk,clkout,clkout1,clkout2);
input rst,clk;
output clkout,clkout1,clkout2;
reg clkout;
reg clk1o;
reg clkout1;
reg clk2o;
reg clkout2;
always@(posedge clk)
if(!rst)
clkout2<=0;
else
clkout2<=(~clk1o)^clkout2;

always@(posedge clk)
if(!rst)
clk1o<=0;
else
clk1o<=clkout2;

always@(negedge clk)
if(!rst)
clkout1<=0;
else
clkout1<=(~clk2o)^clkout1;

always@(negedge clk)
if(!rst)
clk2o<=0;
else
clk2o<=clkout1;

always@(clkout1 or clkout2 or rst)
if(!rst)
clkout=0;
else
clkout=clkout2|clkout1; 
endmodule