LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY portaout IS
   PORT(
      RESET       : IN std_logic;
      CLK         : IN std_logic;
      DIN         : IN std_logic_vector (7 DOWNTO 0);
      PortAOutLd  : IN std_logic;
      PAOUT       : OUT std_logic_vector (7 DOWNTO 0)
   );

END portaout;


ARCHITECTURE rtl OF portaout IS

   SIGNAL    PortAOutRegD : std_logic_vector(7 DOWNTO 0);
   SIGNAL    PortAOutRegQ : std_logic_vector(7 DOWNTO 0);


   BEGIN

      PortAOutRegProc: PROCESS ( PortAOutLd, PortAOutRegQ, DIN )

         BEGIN

            IF ( PortAOutLd = '0')  THEN
               PortAOutRegD     <= DIN;
			ELSE
			   PortAOutRegD     <= PortAOutRegQ;
            END IF;

         END PROCESS;


      PortAOutRegSynchProc: PROCESS ( RESET, CLK )

         BEGIN

            IF (RESET = '1') THEN
               PortAOutRegQ     <= "00000000";
            ELSIF ( CLK'EVENT and CLK = '1')  THEN
               PortAOutRegQ     <= PortAOutRegD;
            END IF;

         END PROCESS;

	  PAOUT <= PortAOutRegQ;

   END rtl;