LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY portain IS
   PORT(
      PAIN       : IN std_logic_vector (7 DOWNTO 0);
      RESET      : IN std_logic;
      CLK        : IN std_logic;
      PortAInLd  : IN std_logic;
      PortAInReg : OUT std_logic_vector (7 DOWNTO 0)
   );

END portain;


ARCHITECTURE rtl OF portain IS

   SIGNAL    PortAInRegQ : std_logic_vector(7 DOWNTO 0);
   SIGNAL    PortAInRegD : std_logic_vector(7 DOWNTO 0);


   BEGIN

	  PortAInReg <= PortAInRegQ;

      PortAInRegProc: PROCESS ( PortAInLd, PAIN, PortAInRegQ )

         BEGIN

            IF ( PortAInLd = '0')  THEN
               PortAInRegD     <= PAIN (7 DOWNTO 0);
			ELSE
               PortAInRegD     <= PortAInRegQ;
            END IF;

      END PROCESS;


      PortAInRegSynchProc: PROCESS ( RESET, CLK )

         BEGIN

            IF (RESET = '1') THEN
               PortAInRegQ     <= "00000000";
            ELSIF ( CLK'EVENT and CLK = '1')  THEN
               PortAInRegQ     <= PortAInRegD;
            END IF;

      END PROCESS;

   END rtl;