Flow report for vga
Sat Dec 18 20:21:49 2004
Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Elapsed Time
  5. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------+
; Flow Summary                                                  ;
+-----------------------+---------------------------------------+
; Flow Status           ; Successful - Sat Dec 18 20:21:45 2004 ;
; Revision Name         ; vga                                   ;
; Top-level Entity Name ; vga                                   ;
; Family                ; ACEX1K                                ;
; Device                ; EP1K30QC208-3                         ;
; Total logic elements  ; 96 / 1,728 ( 5 % )                    ;
; Total pins            ; 10 / 147 ( 6 % )                      ;
; Total memory bits     ; 0 / 24,576 ( 0 % )                    ;
; Total PLLs            ; 0                                     ;
+-----------------------+---------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+------------------------------------------
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 12/18/2004 20:21:27 ;
; Main task         ; Compilation         ;
; Revision Name     ; vga                 ;
+-------------------+---------------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+--------------------------------------
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:03     ;
; Fitter               ; 00:00:08     ;
; Assembler            ; 00:00:02     ;
; Timing Analyzer      ; 00:00:01     ;
; Total                ; 00:00:14     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --import_settings_files=on --export_settings_files=off vga -c vga
quartus_fit --import_settings_files=off --export_settings_files=off vga -c vga
quartus_asm --import_settings_files=off --export_settings_files=off vga -c vga
quartus_tan --import_settings_files=off --export_settings_files=off vga -c vga