JDF F
// Created by Project Navigator ver 1.0
PROJECT Untitled
DESIGN 8051_interface Normal
DEVFAM xpla3
DEVFAMTIME 315558000
DEVICE xcr3064xl
DEVICETIME 315558000
DEVPKG VQ100
DEVPKGTIME 315558000
DEVSPEED -6
DEVSPEEDTIME 315558000
FLOW XST VHDL
FLOWTIME 315558000
STIMULUS uc_interface_tb.vhd Normal
MODULE uc_interface.vhd
MODSTYLE uc_interface Normal
[Normal]
p_ModelSimSimRunTime_tb=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1040406135, 12us
p_ModelSimSimRunTime_tbw=xstvhd, xpla3, Module Bencher Waveform.t_MSimulateBehavioralVhdlModel, 315558000, 1000ns
_PlsClockEnable=xstvhd, xpla3, Schematic.t_synthesize, 973620538, False
_SynthCplxClkEnExtract=xstvhd, xpla3, Schematic.t_synthesize, 1012329270, False
_VhdlSimCustom_behav=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1040406856, func_sim.do
_VhdlSimCustom_postPar=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1040407050, post_sim.do
_VhdlSimDo_behav=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulateBehavioralVhdlModel, 1040406856, False
_VhdlSimDo_postPar=xstvhd, xpla3, Module VHDL Test Bench.t_MSimulatePostPlace&RouteVhdlModel, 1040406862, False
[STATUS-ALL]
uc_interface.ngcFile=WARNINGS,1040407051
uc_interface.postParVHDLSimModel=WARNINGS,1040407051
[STRATEGY-LIST]
Normal=True