library ieee;
use ieee.std_logic_1164.all;
entity kz is
   port(left,right:in std_logic;
        lft,rit,lr:out std_logic);
end kz;
architecture kz_arc of kz is
begin
   process(left,right)
   variable a:std_logic_vector(1 downto 0);
   begin
     a:=left&right;
     case a is 
        when"00"=>lft<='0';
                  rit<='0';
                  lr<='0';
        when"10"=>lft<='1';
                  rit<='0';
                  lr<='0';
        when"01"=>rit<='1';
                  lft<='0';
                  lr<='0';
        when others=>rit<='1';
                     lft<='1';
                     lr<='1';
     end case;
   end process;
end kz_arc;
(2)左邊燈控制模塊
說明：此模塊的功能是當左轉時控制左邊的3個燈，當左右信號都有效時，輸出為全“1”。
library ieee;
use ieee.std_logic_1164.all;
entity lfta is
   port(en,clk,lr:in std_logic;
        l2,l1,l0:out std_logic);
end lfta;
architecture lft_arc of lfta is
begin
   process(clk,en,lr)
   variable tmp:std_logic_vector(2 downto 0);
   begin
      if lr='1' then
         tmp:="111";
      elsif en='0' then
         tmp:="000";
      elsif clk'event and clk='1' then
         if tmp="000" then
            tmp:="001";
         else
            tmp:=tmp(1 downto 0)&'0';
         end if;
      end if;
      l2<=tmp(2);
      l1<=tmp(1);
      l0<=tmp(0);
   end process;
end lft_arc;
 
（2） 右邊燈控制模塊
說明：此模塊的功能是控制右邊的3個燈，與上面模塊相似。
library ieee;
use ieee.std_logic_1164.all;
entity rita is
    port(en,clk,lr:in std_logic;
         r2,r1,r0:out std_logic);
end rita;
architecture rit_arc of rita is
begin
   process(clk,en,lr)
   variable tmp:std_logic_vector(2 downto 0);
   begin
    if lr='1' then
       tmp:="111";
    elsif en='0' then
       tmp:="000";
    elsif clk'event and clk='1' then
       if tmp="000" then
          tmp:="100";
       else
         tmp:='0'&tmp(2 downto 1);
       end if;
    end if;
       r2<=tmp(2);
       r1<=tmp(1);
       r0<=tmp(0);
    
   end process;
end rit_arc;