?? cmp.map.rpt
字號(hào):
Analysis & Synthesis report for cmp
Wed Oct 12 10:28:10 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Oct 12 10:28:10 2005 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; cmp ;
; Top-level Entity Name ; cmp ;
; Family ; MAX7000S ;
; Total macrocells ; 24 ;
; Total pins ; 24 ;
+-----------------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; cmp ; cmp ;
; Family name ; MAX7000S ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+----------------------------------------------------------------------+-----------------+---------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------------------------------------------------+
; cmp.v ; yes ; User Verilog HDL File ; C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盤(pán)/示例程序/Verilog/基礎(chǔ)實(shí)驗(yàn)/四位比較器/cmp.v ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 24 ;
; Total registers ; 0 ;
; I/O pins ; 24 ;
; Parallel expanders ; 8 ;
; Maximum fan-out node ; a[1] ;
; Maximum fan-out ; 12 ;
; Total fan-out ; 115 ;
; Average fan-out ; 2.40 ;
+----------------------+----------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |cmp ; 24 ; 24 ; |cmp ;
+----------------------------+------------+------+---------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Administrator/桌面/program file/CD ROM/7128板子光盤(pán)/示例程序/Verilog/基礎(chǔ)實(shí)驗(yàn)/四位比較器/cmp.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Oct 12 10:28:05 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cmp -c cmp
Info: Found 1 design units, including 1 entities, in source file cmp.v
Info: Found entity 1: cmp
Info: Elaborating entity "cmp" for the top level hierarchy
Warning: Verilog HDL assignment warning at cmp.v(14): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at cmp.v(15): truncated value with size 32 to match size of target (4)
Warning: Output pins are stuck at VCC or GND
Warning: Pin "c[0]" stuck at VCC
Warning: Pin "c[1]" stuck at VCC
Warning: Pin "c[5]" stuck at GND
Warning: Pin "c[6]" stuck at GND
Warning: Pin "en[0]" stuck at GND
Warning: Pin "en[1]" stuck at GND
Warning: Pin "en[2]" stuck at GND
Warning: Pin "en[3]" stuck at GND
Warning: Pin "en[4]" stuck at GND
Warning: Pin "en[5]" stuck at GND
Warning: Pin "en[6]" stuck at GND
Warning: Pin "en[7]" stuck at GND
Info: Implemented 48 device resources after synthesis - the final resource count might be different
Info: Implemented 8 input pins
Info: Implemented 16 output pins
Info: Implemented 24 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings
Info: Processing ended: Wed Oct 12 10:28:10 2005
Info: Elapsed time: 00:00:06
?? 快捷鍵說(shuō)明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號(hào)
Ctrl + =
減小字號(hào)
Ctrl + -