?? add121313.vhd
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY add121313 is
PORT(clk : in STD_LOGIC;
Din1 :in signed (11 downto 0);
Din2 :in signed (12 downto 0);
Dout:out signed(12 downto 0));
END add121313;
ARCHITECTURE a of add121313 is
SIGNAL s1: signed(12 downto 0);
BEGIN
s1<=(Din1(11)&Din1);
PROCESS(Din1,Din2,clk)
BEGIN
if clk'event and clk='1' then
Dout<=s1+Din2;
end if;
end process;
end a;
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